W89C841F Datasheet, PDF (55/102 Pages) Winbond – 3-IN - 1 10/100M FAST ETHERNET CONTROLLER

W89C841F/D
C18/CIMR Interrupt Mask Register, continued
BIT ATTRIBUTE BIT NAME
DESCRIPTION
14
R/W
13
R/W
12
R/W
11
R/W
10
R/W
9
R/W
8
R/W
7
R/W
6
R/W
5
R/W
RPPE
BEE
PIE
TEE
TEIE
EPFE
RIE
RBUE
RINTE
TFUE
Receive Pause Packet Interrupt Enable
The receive pause packet Interrupt will be enabled if both AIE
and BPPE are set to high, otherwise, the receive pause packet
Interrupt will be disabled.
Bus Error Enable
The Bus Error Interrupt will be enabled if both AIE and BEE are
set to high, otherwise, the Bus Error Interrupt will be disabled.
PHY Interrupt Enable.
The PHY Interrupt will be enabled if both AIE and PIE are set to
high, otherwise, the PHY Interrupt will be disabled.
Timer Expired Enable
The Timer Expired Interrupt will be enabled if both AIE and
TEE are set to high, otherwise, the Timer Expired Interrupt will
be disabled.
Transmit Early Interrupt Enable
The Transmit Early Interrupt will be enabled if both AIE and
TEIE are set to high, otherwise, the Transmit Early Interrupt will
be disabled.
EEPROM Programming Fail Enable:
The EEPROM Programming Fail will be enabled if both AIE
and EPFE are set to high, otherwise, the EEPROM
Programming Fail will be disabled.
Receive Idle Enable.
The Receive Idle Interrupt will be enabled if both AIE and RIE
are set to high, otherwise, the Receive Idle Interrupt will be
disabled.
Receive Buffer Unavailable Enable.
The Receive Buffer Unavailable Interrupt will be enabled if both
AIE and RBUE are set to high, otherwise, the Receive Buffer
Unavailable Interrupt will be disabled.
Receive Complete Interrupt Enable
The Receive Interrupt will be enabled if both NIE and RINTE
are set to high, otherwise, the Receive Interrupt will be
disabled.
Transmit FIFO Underflow Enable
The Transmit FIFO Underflow Interrupt will be enabled if both
AIE and TFUE are set to high, otherwise, the Transmit FIFO
Underflow Interrupt will be disabled.
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Publication Release Date: October 18, 2001
Revision A3