W89C841F Datasheet, PDF (11/102 Pages) Winbond – 3-IN - 1 10/100M FAST ETHERNET CONTROLLER

W89C841F/D
PCI Interface, continued
SIGNAL NAME PIN TYP.
C_BEB[3:0]
IO/TS
PAR
IO/TS
FRAMEB
IO/STS
IRDYB
IO/STS
TRDYB
IO/STS
STOPB
IO/STS
PIN NO.
5, 17, 28, 39
27
18
19
22
24
DESCRIPTION
Multiplexed Command and Byte Enables
These signals are driven by current bus master.
During address phase, they mean a bus command.
On the other phase, they present the byte enable of
the transaction.
Parity Signal
This PAR represents the even parity across
AD[31:0] and C_BEB[3:0]. It has the same timing as
AD[31:0] but is delayed by one clock.
PCI Cycle Frame
The current bus master asserts FRAMEB to
indicate the beginning and duration of a bus access.
This signal keeps asserted while the current
transaction is ongoing and keeps deasserted to
indicate that the next data phase is the final data
phase.
Initiator Ready
The IRDYB is asserted by the current initiator to
indicate the ability to complete the data transfer at
the current data phase. The initiator asserts IRDYB
to indicate the valid write data, or to indicate it is
ready to accept the read data. More than or exactly
one wait state will be inserted if IRDYB is
deasserted during the current transaction. Data is
transferred at the clock rising edge when both
IRDYB and TRDYB are asserted at the same time.
Target Ready
Asserted by the current target to indicate ability to
complete data transfer at the current data phase.
When W89C841F is operating at the bus slave
mode, it asserts TRDYB to indicate that the valid
read data presents on the bus or to indicate it is
ready to accept data. Wait states will be inserted if
TRDYB is deasserted. Data is transferred at the
rising edge of the PCI clock when IRDYB and
TRDYB are both asserted at the same time.
PCI Stop
Asserted by the current target to request PCI bus
master to stop the current transaction.
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Publication Release Date: October 18, 2001
Revision A3