W89C841F Datasheet, PDF (51/102 Pages) Winbond – 3-IN - 1 10/100M FAST ETHERNET CONTROLLER

W89C841F/D
C08/CRSDR Receive Start Demand Register
The register is used to request W89C841F to do a receive process.
BIT ATTRIBUTE BIT NAME
DESCRIPTION
31:0
W
RSD
Receive Start Demand
A write to this register will trigger W89C841F receive DMA to
fetch the descriptor for progressing the receiving operation
when W89C841F receive DMA is staying at the suspend
state. Otherwise, the write operation will have no effect.
C0c/CRDLA Receive Descriptors List Addresses
The register defines the start address of the receive descriptor list. It should be updated only when the
receive DMA state machine is staying at the stop state.
BIT ATTRIBUTE BIT NAME
DESCRIPTION
31:2
R/W
SRL
Start address of Receive List
1:0
R/W
MBZ
Must be written as 0 for double word alignment.
C10/CTDLA Transmit Descriptors List Addresses
The register defines the start address of the transmit descriptor list. It should be updated only when the
transmission DMA state machine is staying at the stop state.
BIT ATTRIBUTE BIT NAME
DESCRIPTION
31:2
R/W
STL
Start address of Transmit List
1:0
R/W
MBZ
Must be written as 0 for double word alignment.
C14/CISR Interrupt Status Register
Most bits of this register report the interrupt status. The assertion of the interrupt status, reported by
bits 0 to bit 14 and the corresponding interrupt mask bits will cause a hardware interrupt to the host. A
write with 1 value the status bit will clear them and write 0 will have no effect.
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Publication Release Date: October 18, 2001
Revision A3