W89C841F Datasheet, PDF (50/102 Pages) Winbond – 3-IN - 1 10/100M FAST ETHERNET CONTROLLER

W89C841F/D
C00/CBCR PCI Bus Control Register, continued
BIT ATTRIBUTE BIT NAME
DESCRIPTION
7
R/W
BBE
Buffer With Big Endian
When set, the data buffers are treated with big endian
ordering.
When reset, the data buffers are treated with little endian
ordering.
6:2
R/W
SKIP
Skip Length Between Descriptors
This field specifies the skip length between two descriptors
from the start address of the current descriptor to the start
address of the next descriptor. The unit of the skip length is
double word. The default value after hardware reset is 04h.
1
R/W
ARB
Arbitration Between Tx and Rx Processes
When reset, the TX process and RX process will have the
right to use the internal bus with the same priority.
When set, the RX process will have higher priority than TX
process with regarding to the internal bus utilization.
0
R/W
SWR
Software Reset.
Set bit SW_Reset to high will reset most internal registers
except registers C34/CMA0, C38/CMA1, D00/DWUPC −
D6c /DBWF4BM3, Dcc/CPA0, Dd0/CPA1, Df0/DFER − Dfc
/DFFER and PCI Configuration Registers.
C04/CTSDR Transmit Start Demand Register
This register is used to request W89C841F to do a transmission process.
BIT ATTRIBUTE BIT NAME
DESCRIPTION
31:0
W
TSD
Transmit Start Demand
A write to this register will trigger W89C841F transmit DMA
to fetch the descriptor for progressing the transmission
operation when W89C841F transmit DMA is staying at the
suspend state. Otherwise, the write operation will have no
effect.
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