W89C841F Datasheet, PDF (54/102 Pages) Winbond – 3-IN - 1 10/100M FAST ETHERNET CONTROLLER

W89C841F/D
C14/CISR Interrupt Status Register, continued
BIT ATTRIBUTE BIT NAME
4
R/WC
RERR
3
R/WC
REI
2
R/WC
TBU
1
R/WC
TIDLE
0
R/WC
TINT
DESCRIPTION
Receive Error
A high indicates that the receive DMA detects a receive
error during the packet reception.
Receive Early Interrupt
The REI will be set when the number of the data of the
incoming frame, in double word unit, transferred to the
data buffer reaches Receive Early Interrupt Threshold
specified by the register C1c/CNCR[28:21] if Receive
Early Interrupt On in the register C1c/CNCR[31] is set.
Transmit Buffer Unavailable
A high indicates that there is no available transmit
descriptor during or after the packet transmission.
Transmit Process in Idle State
A high indicates the transmit state machine is in the idle
state.
Transmit Complete Interrupt
The TINI will be set when a frame transmission is
completed and the FINT (bit 31) of Transmit Descriptor 1
(T01) is set.
C18/CIMR Interrupt Mask Register
The register controls the interrupt enable corresponding to the bits in the register C14/CISR
BIT
31:17
16
15
ATTRIBUTE
R
R/W
R/W
BIT NAME
----
NIE
AIE
DESCRIPTION
Reserved. Fixed to 0.
Normal Interrupt Enable
The Normal Interrupt will be enabled if the NIE is set to
high. The Normal Interrupt is disabled when the NIE is
reset to low. The hardware interrupt will be asserted if both
the NIE bit of the C18/CIMR[16] and the NIR bit of the
C14/CISR[16] are set to high.
Abnormal Interrupt Enable
The Abnormal Interrupt will be enabled if the AIE is set to
high. The Abnormal Interrupt is disabled when the AIE is
reset to low. The hardware interrupt will be asserted if both
the AIE bit of the C18/CIMR[15] and the AIR bit of the
C14/CISR[15] are set to high.
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