W89C841F Datasheet, PDF (75/102 Pages) Winbond – 3-IN - 1 10/100M FAST ETHERNET CONTROLLER

W89C841F/D
Dc8/DMMAR MII Management Access Register, continued
BIT
28:26
25:21
20:16
15:0
ATTRIBUTE
R
R/W
R/W
R/W
BIT NAME
-----
PHYADD
REGADD
REGData
DESCRIPTION
Reserved. Fixed to 0
PHY Address
The PHY address must be the same as internal
transceiver’s PHY address setting. Deafult to 01h.
PHY’s Register Address
Refer to MII Management Registers to access the
dedicated register.
PHY Register Data
PHY Register Data is used to store the read/write data for
MII management registers in embedded transceiver.
Dcc/DPA0 Physical Address Register 0
The register defines the first 32 bits of the 48 bits MAC address. The DPA0 value is loaded from
EEPROM after hardware reset
BIT
31:24
23:16
15:8
7:0
ATTRIBUTE
R/W
R/W
R/W
R/W
BIT NAME
PAR3
PAR2
PAR1
PAR0
DESCRIPTION
Physical Address 3
The PAR3 defines the bit 24 − 31 of the MAC address.
Physical Address 2
The PAR2 defines the bit 16 − 23 of the MAC address.
Physical Address 1
The PAR1 defines the bit 8 − 15 of the MAC address.
Physical Address 0
The PAR0 defines the bit 0 − 7 of the MAC address.
Dd0/DPA1 Physical Address Register 1
The register defines the last 16 bits of the 48 bits MAC address. The DPA1 value is loaded from
EEPROM after hardware reset
BIT
31:16
15:8
7:0
ATTRIBUTE
R
R/W
R/W
BIT NAME
---
PAR5
PAR4
DESCRIPTION
Reserved. Fixed at 0.
Physical Address 5
The PAR5 defines the 40 − 47 bit of the 48 bit of the MAC
address.
Physical Address 4
The PAR0 defines the 32 − 39 bit of the 48 bit of the MAC
address.
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Publication Release Date: October 18, 2001
Revision A3