W89C841F Datasheet, PDF (37/102 Pages) Winbond – 3-IN - 1 10/100M FAST ETHERNET CONTROLLER

W89C841F/D
F04/FCS Command and Status Register, continued
BIT
23
22:21
20
19:9
8
7
6
5:3
2
1
0
ATTRIBUTE
R
R
R
R
R/W
R
R/W
R
R/W
R/W
R/W
BIT NAME
FBTBC
---
CAPS
---
SE
----
PER
---
BM
MS
IOS
DESCRIPTION
Fast Back-to-Back Capable
Fixed at 1. Indicates the capability of accepting fast back to
back transactions which are not accessing to the same
target.
Reserved. Fixed at 0.
Capabilities List
The value is dependent on the PMEn and VPDEn loaded
from EEPROM to decide the W89C841F power
management and Vital Product Data capability. While CAPS
is equal to
1: indicates that W89C841F supports the PCI Power
Management and/or VPD.
0: indicates that W89C841F does not support Power
Management and VPD.
Reserved. Fixed at 0.
SERRB Enable
Set SE bit high to enable W89C841F to assert SERRB if an
address parity error is detected. This bit and bit PER must
be set 1 to signal SERR event.
Reserved. Fixed at 0.
Parity Error Response
Set PER bit to high to enable the W89C841F to respond to
parity error. When PER is reset, W89C841F will ignore any
parity error and continue the normal operation. W89C841F
internal parity checking and generation function will not be
disabled even PER is reset.
Reserved. Fixed at 0.
Bus Master
Set BM bit to high will allow W89C841F acting as a bus
master. Reset BM bit to low will disable the W89C841F bus
master ability.
Memory Space
Set MS bit to high will allow W89C841F to respond to
memory space access by the host.
I/O Space
Set IOS bit to high will allow W89C841F to respond to I/O
space access by the host.
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Publication Release Date: October 18, 2001
Revision A3