W89C841F Datasheet, PDF (61/102 Pages) Winbond – 3-IN - 1 10/100M FAST ETHERNET CONTROLLER

W89C841F/D
C34/CMA0 Multicast Address Register 0
The register defines the lower 32 bits of the total 64 bits multicast address hashing table.
BIT
31:24
23:16
15:8
7:0
ATTRIBUTE
R/W
R/W
R/W
R/W
BIT NAME
MAR3
MAR2
MAR1
MAR0
DESCRIPTION
Muticast Address 3
The MAR3 defines the bit 31 − 24 of the hashing table.
Muticast Address 2
The MAR2 defines the bit 23 − 16 of the hashing table.
Muticast Address 1
The MAR1 defines the bit 15 − 8 of the hashing table.
Muticast Address 0
The MAR0 defines the bit 7 − 0 of the hashing table.
C38/CMA1 Multicast Address Register 1
The register defines the upper 32 bits of the 64 bits multicast address hashing table.
BIT
31:24
23:16
15:8
7:0
ATTRIBUTE
R/W
R/W
R/W
R/W
BIT NAME
MAR7
MAR6
MAR5
MAR4
DESCRIPTION
Muticast Address 7
The MAR7 defines the bit 63 − 56 of the hashing table.
Muticast Address 6
The MAR2 defines the bit 55 − 48 of the hashing table.
Muticast Address 5
The MAR1 defines the bit 47 − 40 of the hashing table.
Muticast Address 4
The MAR4 defines the bit 39 − 32 of the hashing table.
C3c/CGTR General Timer Register
The register shows the real time content of W89C841F internal general timer.
BIT ATTRIBUTE BIT NAME
DESCRIPTION
31
R/W
ATLP Accept Too Long Packet
When set, a packet whose length is longer than 1518 (1522)
bytes is received. When reset, a packet whose length is
longer than 1518 (1522) bytes is not received. Default to 0.
30:17
R
---
Reserved. Fixed at 0.
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Publication Release Date: October 18, 2001
Revision A3