W89C841F Datasheet, PDF (56/102 Pages) Winbond – 3-IN - 1 10/100M FAST ETHERNET CONTROLLER

W89C841F/D
C18/CIMR Interrupt Mask Register, continued
BIT ATTRIBUTE BIT NAME
DESCRIPTION
4
R/W
RERRE Receive Error Enable
The Receive Error Interrupt will be enabled if both AIE and
RERRE are set to high, otherwise, the Receive Error
Interrupt will be disabled.
3
R/W
REIE Receive Early Interrupt Enable
The Receive Early Interrupt will be enabled if both AIE and
REIE are set to high, otherwise, the Receive Early Interrupt
will be disabled.
2
R/W
TBUE Transmit Buffer Unavailable Enable
The Transmit Buffer Unavailable Interrupt will be enabled if
both NIE and TBUE are set to high, otherwise, the Transmit
Buffer Unavailable Interrupt will be disabled.
1
R/W
TIE
Transmit Idle Enable
The Transmit Idle Interrupt will be enabled if both AIE and
TIE are set to high, otherwise, the Transmit Idle Interrupt will
be disabled.
0
R/W
TINTE Transmit Complete Interrupt Enable
The Transmit Interrupt will be enabled if both NIE and TINTE
are set to high, otherwise, the Transmit Interrupt will be
disabled.
C1c/CNCR Network Configuration Register
The register defines the configuration for the data transmission or reception and the interrupt algorithm
for interrupt assertion.
BIT ATTRIBUTE BIT NAME
DESCRIPTION
31
R/W
REIO Receive Early Interrupt On
The receive early interrupt function will be enabled when the
REIO is set to high. Otherwise, receive early interrupt
function will be disabled.
30
R/W
TEIO Transmit Early Interrupt On
The transmit early interrupt function will be enabled when
the TEIO is set to high. Otherwise, transmit early interrupt
function will be disabled.
29
R
ES
Ethernet Speed
1: 100 Mbps
0: 10 Mbps.
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