W89C841F Datasheet, PDF (12/102 Pages) Winbond – 3-IN - 1 10/100M FAST ETHERNET CONTROLLER

W89C841F/D
PCI Interface, continued
SIGNAL NAME
IDSEL
PIN TYP.
I
DEVSELB
IO/STS
REQB
GNTB
O/TS
I/TS
PERRB
IO/STS
PIN NO.
6
23
121
120
25
DESCRIPTION
PCI Initialization Device Select
A. Normal and MAC mode
Asserted by host to signal the configuration access
request to W89C841F.
B. PHYceiver mode
This pin should be pulled to low.
PCI Device Select
Asserted by the current target to indicate that it has
finished decoding its address as the current access
target. When W89C841F is the current master, it
checks if the target asserted this signal within 5 PCI
clocks after having issued command. If not,
W89C841F will abort the access operation,
releases PCI bus access right and acts no more
bus master. When W89C841F is the target, it
asserts DEVSELB in a medium speed, i.e., within 2
clocks.
PCI Request
Asserted by W89C841F to request bus ownership.
REQB will be tri-stated when RSTB asserted.
PCI Grant
A. Normal and MAC mode
Asserted by host to grant that W89C841F have got
the bus ownership. When RSTB asserted,
W89C841F will ignore GNTB.
B. PHYceiver mode
This pin should be pulled to high.
PCI Parity Error
Asserted by the current data receiptor. When
W89C841F acts the bus master, if a data parity
error is detected and the parity error response bit
(F04/FCS[6]) is also set, it will set both bits of
F04/FCS[24] and C14/CISR[13] as 1 to terminate
the current transaction after the current data phase
is finished. When W89C841F acts the target, if a
data parity error is detected and the bit F04/FCS[6]
is set, it will assert PERRB only.
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