W89C841F Datasheet, PDF (36/102 Pages) Winbond – 3-IN - 1 10/100M FAST ETHERNET CONTROLLER

W89C841F/D
F04/FCS Command and Status Register
The F04/FCS comprises two parts, one is the command register (FCS[15:0]) which provides the
control of PCI activity, and another is the status register (FCS[31:16]) which shows the status
information of PCI event. Writing 1 to the bits of the status register will clear them; writing 0 has no
effect.
BIT
31
30
29
28
27
26:25
24
ATTRIBUTE
R/WC
R/WC
R/WC
R/WC
R/WC
R
R/WC
BIT NAME
DPE
SSE
RMA
RTA
STA
DT
MDPE
DESCRIPTION
Detected Parity Error
The DPE bit will be set if a parity error is detected by
W89C841F even the parity error response bit of register
F04/FCS[6] is disabled.
Signaled System Error
The SSE bit will be set if W89C841F assert SERRB.
Received Master Abort
The RMA bit will be set if W89C841F master transaction is
terminated by a master abort.
Received Target Abort
The RTA bit will be set if W89C841F master transaction is
terminated by a target abort.
Signaled Target Abort
The STA bit will be set if W89C841F slave transaction takes
a target abort.
DEVSELB Timing
Fixed at 01b. Indicate a medium DEVSEL# assert timing.
Master Data Parity Error
The MDPE bit will be set if the following three conditions are
met:
1). W89C841F asserts PERRB (on a read) or observes
PERRB asserted (on a write).
2). W89C841F acts as a master in the transaction that the
error occurs.
3). The parity error response bit of register F04/FCS[6] is
set.
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