W89C841F Datasheet, PDF (53/102 Pages) Winbond – 3-IN - 1 10/100M FAST ETHERNET CONTROLLER

W89C841F/D
C14/CISR Interrupt Status Register, continued
BIT ATTRIBUTE BIT NAME
14
R/WC
RPP
13
R/WC
BE
12
R
PI
11
R/WC
TE
10
R/WC
TEI
9
R/WC
EPF
8
R/WC
RIDLE
7
R/WC
RBU
6
R/WC
RINT
5
R/WC
TUF
DESCRIPTION
Receive Pause Packet Interrupt
A high indicates a pause packet is received.
Bus Error Interrupt
A high indicates a bus error happened. The error type will
be shown by bit 25 − 23.
PHY Interrupt
A high indicates a PHY interrupt happened. PHY interrupt
event is stored in Global Interrupt Status Register [address
14h] of MII Management. After reading Global Interrupt
Status Register, that register and this bit will be cleared.
Timer Expired Interrupt
A high indicates the general timer of register C3c/CGTR
expired.
Transmit Early Interrupt
W89C841F will has Transmit Early Interrupt status set
after the packet to be transmitted is completely transferred
into the transmit FIFO if Transmit Early Interrupt On bit of
C1c/CNCR[30] is set. The TEI will be cleared
automatically after the packet is transmitted out from the
transmit FIFO completely.
EEPROM Programming Fail Interrupt
A high indicates a programming error happened when
W89C841F tries to write data into EEPROM that is in write
protected state.
Receive in Idle State
Set means the receive DMA state machine is in the idle
state.
Receive Buffer Unavailable
When there is no receive buffer available, this bit is set
and the receive process enters the suspend state.
Receive Complete Interrupt
A high indicates that a frame has been received and the
receive status is transferred into the receive descriptors of
the current frame.
Transmit FIFO Under-flow
A high indicates that the transmit FIFO had an under-flow
error during the packet transmission.
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Publication Release Date: October 18, 2001
Revision A3