W89C841F Datasheet, PDF (59/102 Pages) Winbond – 3-IN - 1 10/100M FAST ETHERNET CONTROLLER

W89C841F/D
C1c/CNCR Network Configuration Register, continued
BIT ATTRIBUTE BIT NAME
DESCRIPTION
2
R/W
RXON Receive On.
When set, the receive process will be started. When reset,
the receive state machine will be stopped after the current
frame is completed.
1
R/W
TFCEN TX Flow Control Enable
1: W89C841F can transmit Pause packet.
0: W89C841F can not transmit Pause packet. (default)
0
R/W
RFCEN RX Flow Control Enable
1: W89C841F can parse Pause packet.
0: W89C841F can not parse Pause packet. (default)
C20/CFDCR Frame Discarded Counter Register
The register records the missed packet count and the FIFO overflow count.
BIT
31
30:16
15
14:0
ATTRIBUTE
RC
RC
RC
RC
BIT NAME
MRFO
RFOC
MMP
MPC
DESCRIPTION
More Receive FIFO Overflow
This bit is the overflow bit of the receive FIFO Overflow
counter. The actual number of the FIFO overflow must be
more than the number shown by the bits RFOC if the MRFO
is set to high. This bit will be clear after read.
Receive FIFO Overflow Counter
The RFOC indicates the number of the packets that are
discarded due to the receive FIFO overflow under the
condition of the receive buffer is not available. This counter
will be clear after read.
More Missed Packets
Overflow bit of Missed Packet Counter. The actual number
of the missed packet must be more than the number shown
by the bits field MPC if MMP is set tot high. This bit will be
clear after read.
Missed Packet Counter
The MPC indicates the number of packets that are discarded
due to the receive FIFO overflow. This counter will be clear
after read.
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Publication Release Date: October 18, 2001
Revision A3