 English |
|
|
|
|
|
|
|
| TLK105_16 Datasheet, PDF (93/104 Pages) Texas Instruments – TLK105 TLK106 Industrial Temp, Single Port 10/100Mbs Ethernet Physical Layer | |||
| |||
| ◁ |
www.ti.com
TLK105
TLK106
SLLSEB8C â AUGUST 2012 â REVISED APRIL 2016
9.10.22 10Mbs Internal Loopback Timing
Table 9-22. 10Mbs Internal Loopback Timing
PARAMETER
t1
TX_EN to RX_DV Loopback
TEST CONDITIONS
10Mbs internal loopback mode
MIN TYP MAX UNIT
1.7
μs
TX_CLK
TX_EN
TXD[3:0]
CRS
t1
RX_CLK
RX_DV
RXD[3:0]
(1) Measurement is made from the first rising edge of TX_CLK after assertion of TX_EN.
(2) Analog loopback was used. Looping the TX to RX at the analog input/output stage.
T0362-01
Figure 9-22. 10Mbs Internal Loopback Timing
9.10.23 RMII Transmit Timing
Table 9-23. RMII Transmit Timing
PARAMETER
t1
XI Clock Period
t2
TXD[1:0] and TX_EN data setup to X1 rising
t3
TXD[1:0] and TX_EN data hold to X1 rising
t4
XI Clock to PMD Output Pair Latency
TEST CONDITIONS
50MHz Reference
Clock
VDD_IO = 3.3V
VDD_IO = 2.5V
MIN TYP MAX UNIT
20
1.4
ns
2.0
4.9
12
bits
XI
TXD[1:0]
TX_EN
PMD Output Pair
t1
t2
t3
Valid Data
t4
Symbol
Figure 9-23. RMII Transmit Timing
Copyright © 2012â2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TLK105 TLK106
Electrical Specifications
93
|
▷ |
German
Russian
Spanish
Italian
Polish
Chinese
Japanese
Korean
French
Portuguese