TLK105_16 Datasheet, PDF (61/104 Pages) Texas Instruments – TLK105 TLK106 Industrial Temp, Single Port 10/100Mbs Ethernet Physical Layer

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TLK105
TLK106
SLLSEB8C – AUGUST 2012 – REVISED APRIL 2016
8.1.17 MII Interrupt Status Register 2 (MISR2)
This register contains events status and enables for the interrupt function. If an event has occurred since
the last read of this register, the corresponding status bit will be set. If the corresponding enable bit in the
register is set, an interrupt will be generated if the event occurs. The PHYSCR register (0x0011) bits 1 and
0 must also be set to allow interrupts. The status indications in this register will be set even if the interrupt
is not enabled.
Table 8-21. MII Interrupt Status Register 2 (MISR2), address 0x0013
BIT
NAME
15 RESERVED
14 AN Error INT
13 Page Rec INT
12 Loopback FIFO OF/UF INT
11 MDI Crossover Changed INT
10 Sleep Mode INT
9 Polarity Changed INT
8 Jabber Detect INT
7 RESERVED
6 AN Error EN
5 Page Rec EN
4 Loopback FIFO OF/UF EN
3 MDI Crossover Changed EN
2 Sleep Mode Event EN
1 Polarity Changed EN
0 Jabber Detect EN
DEFAULT
0, RO
0,RO, COR
0,RO, COR
0,RO, COR
0,RO, COR
0,RO, COR
0,RO, COR
0,RO
0,RW
0,RW
0,RW
0,RW
0,RW
0,RW
0,RW
0,RW
DESCRIPTION
RESERVED: Writes ignored, read as 0.
Auto-Negotiation Error Interrupt:
1 = Auto-negotiation error interrupt is pending
0 = No Auto-negotiation error event pending
Page Receive Interrupt:
1 = Page has been received
0 = Page has not been received
Loopback FIFO Overflow/Underflow Event Interrupt:
1 = FIFO Overflow/Underflow event interrupt pending
0 = No FIFO Overflow/Underflow event pending
MDI/MDIX Crossover Status Changed Interrupt:
1 = MDI crossover status changed interrupt is pending
0 = MDI crossover status has not changed
Sleep Mode Event Interrupt:
1 = Sleep Mode event interrupt is pending
0 = No sleep mode event pending
Polarity Changed Interrupt:
1 = Data polarity changed interrupt pending
0 = No Data polarity event pending
Jabber Detect Event Interrupt:
1 = Jabber detect event interrupt pending
0 = No Jabber detect event pending
RESERVED: Writes ignored, read as 0
Enable Interrupt on Auto-Negotiation error event
Enable Interrupt on page receive event
Enable Interrupt on loopback FIFO overflow/underflow event
Enable Interrupt on change of MDI/X status
Enable Interrupt sleep mode event
Enable Interrupt on change of polarity status
Enable Interrupt on Jabber detection event
8.1.18 False Carrier Sense Counter Register (FCSCR)
This counter provides information required to implement the "False Carriers" attribute within the MAU
managed object class of Clause 30 of the IEEE 802.3u specification.
Table 8-22. False Carrier Sense Counter Register (FCSCR), address 0x0014
BIT NAME
15:8 RESERVED
7:0 FCSCNT
DEFAULT
0000 0000, RO
0,RO / COR
DESCRIPTION
RESERVED: Writes ignored, read as 0
False Carrier Event Counter:
This 8-bit counter increments on every false carrier event. This counter stops when it
reaches its maximum count (FFh). When the counter exceeds half full (7Fh), an interrupt
event is generated. This register is cleared on read.
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