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| TLK105_16 Datasheet, PDF (91/104 Pages) Texas Instruments – TLK105 TLK106 Industrial Temp, Single Port 10/100Mbs Ethernet Physical Layer | |||
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TLK105
TLK106
SLLSEB8C â AUGUST 2012 â REVISED APRIL 2016
9.10.19 Auto-Negotiation Fast Link Pulse (FLP) Timing
Table 9-19. Auto-Negotiation Fast Link Pulse (FLP) Timing
PARAMETER
t1
Clock Pulse to Clock Pulse Period
t2
Clock Pulse to Data Pulse Period
t3
Clock, Data Pulse Width
t4
FLP Burst to FLP Burst Period
t5
Burst Width
TEST CONDITIONS
Data = 1
MIN TYP MAX UNIT
125
μs
62
μs
114
ns
16
ms
2
ms
t1
t2
t3
t3
Fast Link Pulse(s)
Clock
Pulse
t5
Data
Pulse
t4
Clock
Pulse
FLP Burst
FLP Burst
T0359-01
Figure 9-19. Auto-Negotiation Fast Link Pulse (FLP) Timing
9.10.20 100Base-TX Signal Detect Timing
Table 9-20. 100Base-TX Signal Detect Timing
PARAMETER
t1
SD Internal Turn-on Time
t2
Internal Turn-off Time
TEST CONDITIONS
MIN TYP MAX UNIT
100 μs
200 μs
PMD Input Pair
t1
t2
SD+ Intermal
NOTE: The signal amplitude on PMD Input Pair must be TP-PMD compliant.
Figure 9-20. 100Base-TX Signal Detect Timing
T0360-01
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