TLK105_16 Datasheet, PDF (4/104 Pages) Texas Instruments – TLK105 TLK106 Industrial Temp, Single Port 10/100Mbs Ethernet Physical Layer

TLK105
TLK106
SLLSEB8C – AUGUST 2012 – REVISED APRIL 2016
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2 Pin Descriptions
The TLK10x pins fall into the following interface categories (subsequent sections describe each interface):
• Serial Management Interface
• MAC Data Interface
• Clock Interface
• LED Interface
• Reset and Power Down
• Bootstrap Configuration Inputs
• 10/100Mbs PMD Interface
• Special Connect Pins
• Power and Ground pins
Note: Configuration pin option. See Section 3.1 for Jumper Definitions.
The definitions below define the functionality of each pin.
Type: I Input
Type: O Output
Type: I/O Input/Output
Type: OD
Open Drain
Type: PD, PU Internal Pulldown/Pullup
Type: S
Configuration Pin (All configuration pins have weak internal
pullups or pulldowns. Use an external 2.2kΩ resistor if you
need a different default value. See Section 3.1 for details.)
2.1 Pin Layout
RXD_3 / PHYAD4
TX_CLK
TX_EN
TXD_0
TXD_1
TXD_2
TXD_3
INT / PWDN
32 31 30 29 28 27 26 25
1
24
2
23
3
22
4
21
GND
5
20
6
19
7
18
8
17
9 10 11 12 13 14 15 16
PFBIN2
XI
XO
VDD_IO
MDC
MDIO
RESET
LED_LINK / AN_0
Figure 2-1. TLK10x PIN DIAGRAM, TOP VIEW
This document describes signals that take on different names depending on configuration. In such cases,
the different names are placed together and separated by slash (/) characters. For example, "RXD_3 /
PHYAD4". Active low signals are represented by overbars.
.
4
Pin Descriptions
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