TLK105_16 Datasheet, PDF (80/104 Pages) Texas Instruments – TLK105 TLK106 Industrial Temp, Single Port 10/100Mbs Ethernet Physical Layer

TLK105
TLK106
SLLSEB8C – AUGUST 2012 – REVISED APRIL 2016
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9.10 AC Specifications
9.10.1 Power Up Timing
Table 9-1. Power Up Timing
PARAMETER
TEST CONDITIONS
MIN TYP MAX UNIT
Time from powerup to hardware-configuration pin
t₁
transition to output-driver function, using internal
POR (RESET pin tied high)
100 270
ms
t₂
XI Clock initialization
XI Clock must be stable for minimum of 1µs
prior to configuration.
1
µs
VDD
Hardware RESET
t1
Dual function pins
t2
Become enabled
As outputs
XI Clock
Figure 9-1. Power Up Timing
NOTE
It is important to choose pullup and-or pulldown resistors for each of the hardware
configuration pins that provide fast RC time constants in order to latch in the proper value
prior to the pin transitioning to an output driver.
9.10.2 Reset Timing
PARAMETER
t₁
RESET pulse width
Table 9-2. Reset Timing
TEST CONDITIONS
XI Clock must be stable for minimum of 1µs
during RESET pulse low time.
MIN TYP MAX UNIT
1
µs
80
Electrical Specifications
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