TLK105_16 Datasheet, PDF (37/104 Pages) Texas Instruments – TLK105 TLK106 Industrial Temp, Single Port 10/100Mbs Ethernet Physical Layer

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TLK105
TLK106
SLLSEB8C – AUGUST 2012 – REVISED APRIL 2016
PARAMETER
Load Capacitance
Table 7-3. 25MHz Crystal Specification (continued)
TEST CONDITIONS
MIN
10
TYP MAX UNIT
40 pF
7.3 Thermal Vias Recommendation
The following thermal via guidelines apply to DOWN_PAD, pin 33:
1. Thermal via size = 0.2mm
2. Recommend 4 vias
3. Vias have a center to center separation of 2mm.
Adherence to this guideline is required to achieve the intended operating temperature range of the device.
Figure 7-3 illustrates an example layout.
Figure 7-3. Example Layout
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Design Guidelines
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