TLK105_16 Datasheet, PDF (57/104 Pages) Texas Instruments – TLK105 TLK106 Industrial Temp, Single Port 10/100Mbs Ethernet Physical Layer

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TLK105
TLK106
SLLSEB8C – AUGUST 2012 – REVISED APRIL 2016
Table 8-18. PHY Status Register (PHYSTS), address 0x0010 (continued)
BIT NAME
DEFAULT
DESCRIPTION
14 MDI-X Mode 0,RO
MDI-X mode as reported by the Auto-Negotiation state machine:
1 = MDI pairs swapped (Receive on TPTD pair, Transmit on TPRD pair)
0 = MDI pairs normal (Receive on TRD pair, Transmit on TPTD pair)
This bit will be affected by the settings of the AMDIX_EN and FORCE_MDIX bits in the PHYCR
register. When MDIX is enabled, but not forced, this bit will update dynamically as the Auto-MDIX
algorithm swaps between MDI and MDI-X configurations.
13 Receive Error 0,RO/LH Receive Error Latch:
Latch
1 = Receive error event has occurred since last read of RXERCNT register (0x0015)
0 = No receive error event has occurred
This bit will be cleared upon a read of the RECR register
12 Polarity Status 0,RO
Polarity Status:
1 = Inverted Polarity detected
0 = Correct Polarity detected
This bit is a duplication of bit 4 in the 10BTSCR register (0x001A). This bit will be cleared upon a read
of the 10BTSCR register, but not upon a read of the PHYSTS register.
11 False Carrier 0,RO/LH False Carrier Sense Latch:
Sense Latch
1 = False Carrier event has occurred since last read of FCSCR register (0x0014)
0 = No False Carrier event has occurred
This bit will be cleared upon a read of the FCSR register.
10 Signal Detect 0,RO/LL Signal Detect:
Active high 100Base-TX unconditional Signal Detect indication from PMD
9 Descrambler
Lock
0,RO/LL
Descrambler Lock:
Active high 100Base-TX Descrambler Lock indication from PMD
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