TLK105_16 Datasheet, PDF (40/104 Pages) Texas Instruments – TLK105 TLK106 Industrial Temp, Single Port 10/100Mbs Ethernet Physical Layer

TLK105
TLK106
SLLSEB8C – AUGUST 2012 – REVISED APRIL 2016
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Table 8-2. Register Table
Register Name
Basic Mode Control
Register
Addr
00h
Basic Mode Status
01h
Register
PHY Identifier
02h
Register 1
PHY Identifier
03h
Register 2
Auto-Negotiation
04h
Advertisement
Register
Auto-Negotiation Link 05h
Partner Ability
Register (Base Page)
Auto-Negotiation
06h
Expansion Register
Auto-Negotiation Next 07h
Page TX Register
Auto-Negotiate Link
08h
Partner Ability Page
Register
Control Register 1
09h
Control Register 2
0Ah
Control Register 3
0Bh
RESERVED
0Ch
Register Control
0Dh
Register
Address or Data
0Eh
Register
RESERVED
0Fh
PHY Status Register 10h
PHY Specific Control
Register
11h
MII Interrupt Status
Register 1
12h
MII Interrupt Status
Register 2
13h
MII Interrupt Control
Register
14h
Tag
BMCR
BMSR
Bit 15
Reset
Bit 14
Loopback
Bit 13
Speed
Selection
100Base - 100Base - 100Base -
T4
TX FDX TX HDX
Bit 12
Auto-Neg
Enable
10Base-T
FDX
Bit 11
IEEE
Power
Down
10Base-T
HDX
PHYIDR 1
Bit 10
Isolate
Bit 9
Restart
Auto-Neg
Bit 8
Duplex
Mode
Bit 7
Collision
Test
Bit 6
Bit 5
Bit 4
Bit 3
Reserved
Bit 2
Bit 1
Reserved
OUI MSB
MF
Preamble
Suppress
Auto-Neg
Complete
Remote
Fault
Auto-Neg Link Status
Ability
Jabber
Detect
Bit 0
Extended
Capability
PHYIDR 2
OUI LSB
VNDR_ MDL
MDL_ REV
ANAR
Next Page Reserved Remote Reserved ASM_DI R PAUSE
Ind
Fault
100B-T4
100B-
TX_FD
100B-TX 10B-T_FD
10B-T
Protocol Selection[4:0]
ANLPAR Next Page
Ind
ACK
Remote Reserved ASM_DI R PAUSE
Fault
100B-T4
100B-
TX_FD
100B-TX 10B-T_FD
10B-T
Protocol Selection[4:0]
ANER
Reserved
ANNPTR
ANLNPTR
Next Page Reserved
Ind
Next Page Reserved
Ind
Message
Page
Message
Page
ACK2
ACK2
TOG_TX
Toggle
CODE
CODE
PDF
LP_NP_ NP_ ABLE PAGE_ RX LP_AN_AB
ABLE
LE
CR1
CR2
CR3
Reserved
REGCR
Function
Reserved
Reserved
Reserved
RMII
Enhance
Mode
Reserved
TDR Auto Link Loss
Run
Recovery
Reserved
Fast Auto Robust Fast AN
MDI/X Auto MDI/X Enable
Fast Link- Extended Enhance
Up in PD FD Ability LED Link
Polarity
Swap
MDI/X
Swap
Reserved
Fast AN Select
Fast RXDV Reserved
Detect
Isolate MII
in 100BT
HD
RXERR
During
IDLE
Odd Nibble
Detect
Disable
Fast Link Down Sel
RMII
Receive
Clock
DEVICE ADDRESS
ADDAR
Addr/ Data
Reserved
PHYSTS
PHYSCR
MISR1
MISR2
FCSCR
Reserved
Reserved
MDI-X
Mode
Receive Err
Latch
Polarity
Status
False
Carrier Sen
Latch
Signal
Detect
Descramb Page
Lock
Receive
MII
Interrupt
Remote
Fault
Disable
PLL
Power
Save
Enable
Power Save Mode
Scrambler
Bypass
Reserved
Loopback Fifo Depth
Reserved
Reserved
Link Status
INT
Speed INT
Duplex
Mode INT
Auto-Neg
Comp INT
FC HF INT
RE HF INT
Reserved
Reserved
Auto-Neg
Error INT
Page
Received
INT
Loopback
FIFO O/U
INT
MDI
Crossover
INT
Sleep
Mode INT
Polarity INT Jabber INT
Reserved
Auto-Neg
Error EN
Jabber
Detect
Auto-Neg
Status
COL FD
Enable
Link Status
En
Speed EN
Page
Received
EN
Loopback
FIFO O/U
EN
Loopback
Status
INT POL
Duplex
Mode En
MDI
Crossover
EN
Duplex
Status
Speed
Status
Link Status
TINT
INT_EN INT_OE
Auto-Neg
Comp En
FC HF En RE HF En
Sleep
Mode EN
Polarity EN Jabber EN
Reserved
FCS Count
40
Register Block
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