TLK105_16 Datasheet, PDF (35/104 Pages) Texas Instruments – TLK105 TLK106 Industrial Temp, Single Port 10/100Mbs Ethernet Physical Layer

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TLK105
TLK106
SLLSEB8C – AUGUST 2012 – REVISED APRIL 2016
7 Design Guidelines
7.1 TPI Network Circuit
Figure 7-1 shows the recommended circuit for a 10/100Mbs twisted pair interface. Common mode
chokes on the device side of the transformer are required. Variations with PCB and component
characteristics require that the application be tested to verify that the circuit meets the requirements
of the intended application.
RD±
49.9 :
RD+
49.9 :
Vdd
0.1 PF
Vdd
1 PF
Common mode chokes on the
device side of the transformer
are required.
1:1
RD±
RD+
TD±
49.9 :
49.9 :
TD+
Vdd
1 PF
0.1 PF
Place resistors and capacitors close to the device.
0.1 PF* ^{1:1 T1}
TD±
TD+
RJ45
Note: Center tap is connected to Vdd
* Place capacitors close to the
transformer center taps
All values are typical and are r1%
Copyright © 2016, Texas Instruments Incorporated
Figure 7-1. 10/100Mbs Twisted Pair Interface
7.2 Clock In (XI) Requirements
The TLK10x supports an external CMOS-level oscillator source or an internal oscillator with an external
crystal.
7.2.1 Oscillator
If an external clock source is used, XI should be tied to the clock source and XO should be left floating.
The oscillator should use the same supply voltage as the VDD_IO supply. When operating in RMII, the
oscillator supply voltage must be 3.3V or 2.5V.
Copyright © 2012–2016, Texas Instruments Incorporated
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Design Guidelines
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