TLK105_16 Datasheet, PDF (69/104 Pages) Texas Instruments – TLK105 TLK106 Industrial Temp, Single Port 10/100Mbs Ethernet Physical Layer

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TLK105
TLK106
SLLSEB8C – AUGUST 2012 – REVISED APRIL 2016
8.4 Compliance Test register (COMPTR)
This register allows generation of test patterns for compliance testing.
Table 8-32. Compliance Test register (COMPTR), address 0x0027
BIT
BIT NAME
15:6 RESERVED
5
Test Mode
Select
4:0 Test
Configuration
DEFAULT
0000 0000 00,
RO
0, RW
Writes ignored, read as 0
DESCRIPTION
MSB bit for 100Base-TX test mode. Note: bit 4 must be '0' for 100Base-TX test modes.
0 0000, RW
Bit 4 enables 10Base-T test modes.
1 = 10Base-T test modes
0 = 100Base-TX test modes
For 10Base-T testing, bits [3:0] select the 10Base-T pattern as follows:
0000 = Single NLP
0000 = Single NLP
0001 = Single Pulse 1
0010 = Single Pulse 0
0011 = Repetitive 1
0100 = Repetitive 0
0101 = Preamble (repetitive '10')
0110 = Single 1 followed by TP_IDLE
0111 = Single 0 followed by TP_IDLE
1000 = Repetitive '1001' sequence
1001 = Random 10Base-T data
1010 = TP_IDLE_00
1011 = TP_IDLE_01
1100 = TP_IDLE_10
1101 = TP_IDLE_11
1001 = Random 10Base-T data
For 100Base-TX testing, bits {5,[3:0]} select the transmit sequence. The test mode
transmits a repetitive sequence consisting of a '1' followed by a configurable number of '0'
bits.
Bits {5,[3:0]} define the number of '0' bits that follow the '1'. 1 to 31 '1' bits may be
selected.
0,0001 - 1,1111: single '0' to 31 zeroes
0,0000: Clear the register
Note 1: Bit 4 must be '0' for 100Base-TX test modes.
Note 2: 100Base-T test modes must be cleared before applying a new value. Bits {5,[3:0]}
must be written to 0x0 before configuring a new value.
Note 3: When performing 100Base-TX or 10Base-T tests, the speed must be forced using
the Basic Mode Control Register (BMCR), address 0x0000.
8.5 TX_CLK Phase Shift Register (TXCPSR)
This register allows programming the phase of the MII transmit clock (TX_CLK pin). The TX_CLK has a
fixed phase to the XI pin. However the default phase, while fixed, may not be ideal for all systems,
therefore this register may be used by the system to align the reference clock (XI pin) to the TX_CLK. The
phase shift value is in 4ns units. The phase shift value should be between 0 and 10 (0ns to 40ns). If value
greater than 10 is written, the update value will be the written value modulo 10.
Table 8-33. TX_CLK Phase Shift Register (TXCPSR), address 0x0042
BIT BIT NAME
15:5 RESERVED
4 Phase Shift
Enable
DEFAULT
0000 0000
000, RO
0,RW,SC
RESERVED: Writes ignored, read as 0
DESCRIPTION
TX Clock Phase Shift Enable:
1 = Perform Phase Shift to the TX_CLK according to the value written to Phase Shift Value in bits
[4:0].
0 = No change in TX Clock phase
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