TLK105_16 Datasheet, PDF (59/104 Pages) Texas Instruments – TLK105 TLK106 Industrial Temp, Single Port 10/100Mbs Ethernet Physical Layer

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TLK105
TLK106
SLLSEB8C – AUGUST 2012 – REVISED APRIL 2016
8.1.15 PHY Specific Control Register (PHYSCR)
This register implements the PHY Specific Control register. This register allows access to general
functionality inside the PHY to enable operation in reduced power modes and control interrupt mechanism.
Table 8-19. PHY Specific Control Register (PHYSCR), address 0x0011
BIT NAME
15 Disable PLL
14 PS Enable
13:12 PS Modes
DEFAULT DESCRIPTION
0,RW
Disable PLL:
1 = Disable internal clocks Circuitries
0 = Normal mode of operation
Note: Clock Circuitry can be disabled only in IEEE power-down mode
0,RW
Power Save Modes Enable:
1 = Enable power save modes
0 = Normal mode of operation
00,RW Power Save Modes:
Power Mode
<00>
<01>
<10>
<11>
Name
Normal
IEEE power
down
Active Sleep
Passive
Sleep
Description
Normal operation mode. PHY is fully functional
Low Power mode that shut down all internal circuitry
beside SMI functionality.
Low Power Active Energy Saving mode
that shut down all internal circuitry beside SMI and energy
detect functionalities. In this mode the PHY sends NLP
every 1.4 Sec to wake up link-partner. Automatic power-
up is done when link partner is detected.
Low Power Energy Saving mode
that shut down all internal circuitry beside SMI and energy
detect functionalities. Automatic power-up is done when
link partner is detected.
11 Scrambler
Bypass
0,RW
10 RESERVED 0, RO
9:8 Loopback 01,RW
FIFO Depth
7:5 RESERVED 000, RO
4 COL FD
Enable
0, RW
3 INT POL
1,RW
2 tint
0,RW
Scrambler Bypass:
1 = Scrambler bypass enabled
0 = Scrambler bypass disabled
RESERVED: Writes ignored, read as 0.
Far-End Loopback FIFO Depth:
00 = 4 nibbles FIFO
01 = 5 nibbles FIFO
10 = 6 nibbles FIFO
11 = 8 nibbles FIFO
This FIFO is used to adjust RX (recovered) clock rate to TX clock rate. FIFO depth need to be set
based on expected maximum packet size and clock accuracy. Default value sets to 5 nibbles.
RESERVED: Writes ignored, read as 0.
Collision in Full-Duplex Mode:
1 = Enable generating Collision signaling in Full Duplex
0 = Disable Collision indication in Full Duplex mode. Collision will be active in Half Duplex only.
Interrupt Polarity:
1 = Steady state (normal operation) is 1 logic and during interrupt is 0 logic.
0 = Steady state (normal operation) is 0 logic and during interrupt is 1 logic.
Test Interrupt:
1 = Generate an interrupt
0 = Do not generate interrupt
Forces the PHY to generate an interrupt to facilitate interrupt testing. Interrupts will continue to be
generated as long as this bit remains set.
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