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TLK105_16 Datasheet, PDF (64/104 Pages) Texas Instruments – TLK105 TLK106 Industrial Temp, Single Port 10/100Mbs Ethernet Physical Layer
TLK105
TLK106
SLLSEB8C – AUGUST 2012 – REVISED APRIL 2016
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8.1.21 RMII Control and Status Register (RCSR)
This register configures the RMII Mode of operation. When RMII mode is disabled, the RMII functionality is
bypassed.
Table 8-25. RMII Control and Status Register (RCSR), address 0x0017
BIT NAME
DEFAULT
DESCRIPTION
15:6 RESERVED
0000 0000 00, RO RESERVED: Writes ignored, read as 0.
5 RMII Mode
0, RW, Pin_Strap
RMII Mode Enable: RMII Mode is operational if device powered up in RMII mode
(pin_strap) and 50Mhz clock present. Please note, that in order to switch from RMII to MII
and vise versa, the PHY must initialize after power up in RMII mode (Strap is '1' and
REF_CLK is 50MHz). If the PHY initializes in MII mode, this bit has no effect.
1 = Enable RMII (Reduced MII) mode of operation
0 = Enable MII mode of operation
4 RMII Revision
Select
0, RW
RMII Revision Select:
1 = (RMII revision 1.0) CRS_DV will remain asserted until final data is transferred.
CRS_DV will not toggle at the end of a packet.
0 = (RMII revision 1.2) CRS_DV will toggle at the end of a packet to indicate de-
assertion of CRS.
3 RMII OVFL Status
0, COR
RX FIFO Over Flow Status:
1 = Normal
0 = Overflow detected
2 RMII OVFL Status
0, COR
RX FIFO Under Flow Status:
1 = Normal
0 = Underflow detected
1:0 ELAST_BUF
01, RW
Receive Elasticity Buffer Size:
This field controls the Receive Elasticity Buffer which allows for frequency variation
tolerance between the 50MHz RMII clock and the recovered data. The following values
indicate the tolerance in bits for a single packet. The minimum setting allows for standard
Ethernet frame sizes at ±50ppm accuracy for both RMII and Receive clocks. For greater
frequency tolerance the packet lengths may be scaled (for ±100ppm, divide the packet
lengths by 2).
00 = 14 bit tolerance (up to 16800 byte packets)
01 = 2 bit tolerance (up to 2400 byte packets)
10 = 6 bit tolerance (up to 7200 byte packets)
11 = 10 bit tolerance (up to 12000 byte packets)
64
Register Block
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