TLK105_16 Datasheet, PDF (55/104 Pages) Texas Instruments – TLK105 TLK106 Industrial Temp, Single Port 10/100Mbs Ethernet Physical Layer

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TLK105
TLK106
SLLSEB8C – AUGUST 2012 – REVISED APRIL 2016
8.1.12 Control Register 3 (CR3)
BIT BIT NAME
15:7 RESERVED
6 Polarity
Swap
5 MDI/MDIX
Swap
4 RESERVED
3:0 Fast Link
Down Mode
Table 8-15. Control register 3 (CR3), address 0x000B
DEFAULT
0, RO
0, RW
0, RW
0, RW
0, RW
DESCRIPTION
RESERVED: Writes ignored, read as 0.
Polarity Swap:
1 = Normal polarity
0 = Inverted polarity on both pairs: TPTD+ ↔ TPTD-, TPRD+ ↔ TPRD-
Port Mirror function: To Enable port mirroring, set bit 5 and this bit high.
MDI/MDIX Swap:
1 = Swap MDI pairs (Receive on TPTD pair, Transmit on TPRD pair)
0 = MDI pairs normal (Receive on TPRD pair, Transmit on TPTD pair)
Port Mirror function: To Enable port mirroring, set this bit and bit 6 high.
RESERVED
Fast Link Down Modes:
Bit 3 Drop the link based on RX Error count of the MII interface – When a predefined number
of 32 RX Error occurrences in a 10µs interval is reached, the link will be dropped.
Bit 2 Drop the link based on MLT3 Errors count (Violation of the MLT3 coding in the DSP
output) – When a predefined number of 20 MLT3 Error occurrences in a 10µs interval is
reached, the link will be dropped.
Bit 1 Drop the link based on Low SNR Threshold – When a predefined number of 20
Threshold crossing occurrences in a 10µs interval is reached, the link will be dropped.
Bit 0 Drop the link based on Signal/Energy loss indication – When the Energy detector
indicates Energy Loss, the link will be dropped. Typical reaction time is 10µs.
The Fast Link Down function is an OR of all these 4 options, so the designer can enable
combinations of these conditions.
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