TLK105_16 Datasheet, PDF (42/104 Pages) Texas Instruments – TLK105 TLK106 Industrial Temp, Single Port 10/100Mbs Ethernet Physical Layer

TLK105
TLK106
SLLSEB8C – AUGUST 2012 – REVISED APRIL 2016
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Table 8-3. Register Table, Extended Registers
Register Name
Compliance Test
register
TX_CLK
Voltage Regulator
Control Register
ALCD Control and
Results 1
PowerBack Off
Control Register
Cable Diagnostic
Specific Control
Register 1
Cable Diagnostic
Specific Control
Register 2
Cable Diagnostic
Specific Control
Register 3
Cable Diagnostic
Specific Control
Register 4
Cable Diagnostic
Location Results
Register 1-5
Cable Diagnostic
Amplitude Results
Register 1-5
Cable Diagnostic
General Results
Register
ALCD Control and
Results 2 Register
Addr
27h
Tag
COMPTR
42h
TXCPSR
D0h
VRCR
Bit 15
VRPD
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Reserved
Reserved
Bit 9
Bit 8
Bit 7
Reserved
Bit 6
Bit 5
Bit 4
Test Mode
Select
Phase Shift
En
Bit 3
Bit 2
Bit 1
Test Configuration
Phase Shift Value
155h ALCDRR1 alcd_start
Reserved
alcd_done
alcd_out1
Reserved
alcd_ctrl
AEh PWRBOCR
Reserved
PowerBack Off
Reserved
170h
CDSCR1
Reserved
Cross
Disable
TPTD
Bypass
TPRD
Bypass
Reserved
Average Cycles
Reserved
Bit 0
171h CDSCR2
Reserved
TDR pulse control
173h CDSCR3
Cable length
Reserved
177h CDSCR4
Short cables TH
Reserved
180h
181h
182h
183h
184h
185h
186h
187h
188h
189h
18Ah
215h
CDLRR1
CDLRR2
CDLRR3
CDLRR4
CDLRR5
CDLAR1
CDLAR2
CDLAR3
CDLAR4
CDLAR5
CDGRR
TPTD/RD Peak Location
Reserved
TPTD/RD Peak Amplitude
Reserved
TPTD/RD Peak Amplitude
TPTD Peak TPTD Peak TPTD Peak TPTD Peak TPTD Peak TPRD Peak TPRD Peak TPRD Peak TPRD Peak TPRD Peak
Polarity 5 Polarity 4 Polarity 3 Polarity 2 Polarity 1 Polarity 5 Polarity 4 Polarity 3 Polarity 2 Polarity 1
Cross
Detect on
TPTD
Cross
Detect on
TPRD
Above 5
TPTD
Peaks
Above 5
TPTD
Peaks
Reserved Reserved
ALCDRR2
alcd_out2
alcd_out3
42
Register Block
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