TLK105_16 Datasheet, PDF (43/104 Pages) Texas Instruments – TLK105 TLK106 Industrial Temp, Single Port 10/100Mbs Ethernet Physical Layer

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TLK105
TLK106
SLLSEB8C – AUGUST 2012 – REVISED APRIL 2016
8.1 Register Definition
In the register definitions under the ‘Default’ heading, the following definitions hold true:
• COR = Clear on Read
• Pin_Strap = Default value loads from strapping pin after reset
• LH = Latched High and held until read, based upon the occurrence of the corresponding event
• LL = Latched Low and held until read, based upon the occurrence of the corresponding event
• RO = Read Only access
• RO/COR = Read Only, Clear on Read
• RO/P = Read Only, Permanently set to a default value
• RW = Read Write access
• RW/SC = Read Write Access/Self Clearing bit
• SC = Register sets on event occurrence and Self-Clears when event ends
8.1.1 Basic Mode Control Register (BMCR)
BIT
BIT NAME
15 Reset
Table 8-4. Basic Mode Control Register (BMCR), address 0x0000
DEFAULT
0, RW/SC
DESCRIPTION
PHY Software Reset:
1 = Initiate software Reset / Reset in Process
0 = Normal operation
14 MII Loopback
13 Speed Selection
12 Auto-Negotiation
Enable
11 IEEE Power
Down
10 Isolate
0, RW
1, RW
1, RW
0, RW
0, RW
Writing a 1 to this bit resets the PHY. When the reset operation is done, this bit is cleared to
0 automatically. The configuration is relatched.
MII Loopback:
1 = MII Loopback enabled
0 = Normal operation
When MII loopback mode is activated, the transmitter data presented on MII TXD is looped
back to MII RXD internally.
Speed Select:
When auto-negotiation is disabled writing to this bit allows the port speed to be selected.
1 = 100Mbs
0 = 10Mbs
Auto-Negotiation Enable:
1 = Auto-Negotiation Enabled – bits 8 and 13 of this register are ignored when this bit is
set.
0 = Auto-Negotiation Disabled – bits 8 and 13 determine the port speed and duplex
mode.
Power Down:
1 = Enables IEEE power down mode
0 = Normal operation
Setting this bit powers down the PHY. Only minimal register functionality is enabled during
the power down condition. To control the power down mechanism, this bit is ORed with the
input from the INT/PWDN pin. When the active low INT/PWDN is asserted, this bit is set.
Isolate:
1 = Isolates the Port from the MII with the exception of the serial management
0 = Normal operation
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