TLK105_16 Datasheet, PDF (20/104 Pages) Texas Instruments – TLK105 TLK106 Industrial Temp, Single Port 10/100Mbs Ethernet Physical Layer

TLK105
TLK106
SLLSEB8C – AUGUST 2012 – REVISED APRIL 2016
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RMII function includes a programmable elastic buffer to adjust for the frequency differences between the
reference clock and the recovered receive clock. The programmable elastic buffer minimizes internal
propagation delay based on expected maximum packet size and clock accuracy.
indicates how to program the buffer FIFO based on the expected max packet size and clock accuracy. It
assumes that the RMII reference clock and the far-end transmitter clock have the same accuracy.
START THRESHOLD RBR[1:0]
1(4-bits)
2(8-bits)
3(12-bits)
0(16-bits)
Recommended RMII Packet Sizes
LATENCY TOLERANCE
RECOMMENDED PACKET SIZE RECOMMENDED PACKET SIZE
AT ±50PPM
AT ±100PPM
2 bits
2400 bytes
1200 bytes
6 bits
7200 bytes
3600 bytes
10 bits
12000 bytes
6000 bytes
14 bits
16800 bytes
8400 bytes
4.3 Serial Management Interface
The Serial Management Interface (SMI), provides access to the TLK10x internal register space for status
information and configuration. The SMI is compatible with IEEE802.3-2002 clause 22. The implemented
register set consists of all the registers required by the IEEE802.3-2002, plus several others to provide
additional visibility and controllability of the TLK10x device.
The SMI includes the MDC management clock input and the management MDIO data pin. The MDC clock
is sourced by the external management entity, also called Station (STA), and can run at a maximum clock
rate of 25MHz. MDC is not expected to be continuous, and can be turned off by the external management
entity when the bus is idle.
The MDIO is sourced by the external management entity and by the PHY. The data on the MDIO pin is
latched on the rising edge of the MDC clock. The MDIO pin requires a pull-up resistor (2.2kΩ) which,
during IDLE and turnaround, pulls MDIO high.
Up to 32 PHYs can share a common SMI bus. To distinguish between the PHYs, a 5-bit address is used.
During power-up reset, the TLK10x latches the PHYAD[4:0] configuration pins (Pin 29 to Pin 32) to
determine its address.
The management entity must not start an SMI transaction in the first cycle after power-up reset. To
maintain valid operation, the SMI bus must remain inactive at least one MDC cycle after hard reset is de-
asserted.
In normal MDIO transactions, the register address is taken directly from the management-frame reg_addr
field, thus allowing direct access to 32 16-bit registers (including those defined in IEEE802.3 and vendor
specific). The data field is used for both reading and writing. The Start code is indicated by a <01> pattern.
This pattern makes sure that the MDIO line transitions from the default idle line state. Turnaround is
defined as an idle bit time inserted between the Register Address field and the Data field. To avoid
contention during a read transaction, no device may actively drive the MDIO signal during the first bit of
Turnaround. The addressed TLK10x drives the MDIO with a zero for the second bit of turnaround and
follows this with the required data. Figure 4-3 shows the timing relationship between MDC and the MDIO
as driven/received by the Station (STA) and the TLK10x (PHY) for a typical register read access.
For write transactions, the station-management entity writes data to the addressed TLK10x, thus
eliminating the requirement for MDIO Turnaround. The Turnaround time is filled by the management entity
by inserting <10>. Figure 4-4 shows the timing relationship for a typical MII register write access. The
frame structure and general read/write transactions are shown in Table 4-1, Figure 4-3, and Figure 4-4.
Table 4-1. Typical MDIO Frame Format
MII MANAGEMENT SERIAL PROTOCOL
Read Operation
<IDLE><START><OP CODE><DEVICE ADDR><REG
ADDR><TURNAROUND><DATA><IDLE>
<idle><01><10><AAAAA><RRRRR><Z0><xxxx xxxx xxxx xxxx><idle>
20
Interfaces
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