TLK105_16 Datasheet, PDF (68/104 Pages) Texas Instruments – TLK105 TLK106 Industrial Temp, Single Port 10/100Mbs Ethernet Physical Layer

TLK105
TLK106
SLLSEB8C – AUGUST 2012 – REVISED APRIL 2016
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8.3 PHY Reset Control Register (PHYRCR)
Table 8-31. PHY Reset Control Register (PHYRCR), address 0x001F
BIT BIT NAME
15 Software Reset
14 Software
Restart
13:0 RESERVED
DEFAULT
0, RW,SC
0, RW,SC
00 0000 0000
0000, RO
DESCRIPTION
Software Reset:
1 = Reset PHY. This bit is self cleared and has same effect as Hardware reset pin.
0 = Normal Operation
Software Restart:
1 = Reset PHY. This bit is self cleared and resets all PHY circuitry except the registers.
0 = Normal Operation
Writes ignored, read as 0
68
Register Block
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