TLK105_16 Datasheet, PDF (66/104 Pages) Texas Instruments – TLK105 TLK106 Industrial Temp, Single Port 10/100Mbs Ethernet Physical Layer

TLK105
TLK106
SLLSEB8C – AUGUST 2012 – REVISED APRIL 2016
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Table 8-27. PHY Control Register (PHYCR), address 0x0019 (continued)
BIT NAME
5
LED CFG
DEFAULT
0, RW,
Pin_Strap
LED Configuration Modes:
DESCRIPTION
4:0 PHY ADDR 0000 1, RO
Mode LED_CFG LED_LINK
ON for Good Link
1
1
OFF for No Link
ON for Good Link
2
0
BLINK for Activity
PHY Address:
Strapping configuration for PHY Address.
8.1.24 10Base-T Status/Control Register (10BTSCR)
This register provides the ability to control and read status of the PHY’s internal 10Base-T functionality.
BIT
15:14
13
12:9
8
7
6:5
4
3:1
0
Table 8-28. 10Base-T Status/Control Register (10BTSCR), address 0x001A
NAME
RESERVED
Receiver TH
DEFAULT
000, RO
0, RW
Squelch
0000, RW
RESERVED
NLP Disable
0, RO
0, RW
RESERVED 00, RO
Polarity Status 0, RO
RESERVED 000, RO
Jabber Disable 0, RW
DESCRIPTION
RESERVED: Writes ignored, read as 0.
Lower Receiver Threshold Enable:
1 = Enable 10Base-T lower receiver threshold to allow operation with longer cables
0 = Normal 10Base-T operation
Squelch Configuration:
Used to set the Peak Squelch ‘ON’ threshold for the 10Base-T receiver. Every step is equal to
50mV and allow raising/lowering the Squelch threshold from 200mV to 600mV. The default
Squelch threshold is set to 200mV.
RESERVED: Writes ignored, read as 0.
NLP Transmission Control:
1 = Disable transmission of NLPs
0 = Enable transmission of NLPs
RESERVED: Writes ignored, read as 0.
10Mb Polarity Status:
1 = Inverted Polarity detected
0 = Correct Polarity detected
This bit is a duplication of bit 12 in the PHYSTS register (0x0010). Both bits will be cleared
upon a read of 10BTSCR register, but not upon a read of the PHYSTS register.
RESERVED: Writes ignored, read as 0.
Jabber Disable:
1 = Jabber function disabled
0 = Jabber function enabled
Note: This function is applicable only in 10Base-T
66
Register Block
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