TLK105_16 Datasheet, PDF (14/104 Pages) Texas Instruments – TLK105 TLK106 Industrial Temp, Single Port 10/100Mbs Ethernet Physical Layer

TLK105
TLK106
SLLSEB8C – AUGUST 2012 – REVISED APRIL 2016
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While in MII Loopback mode, there is no link indication, but packets propagate back to the MAC. While in
MII Loopback mode the data is looped back, and can also be transmitted onto the media. For transmitting
data during MII loopback in 100BT only please use bit [6] in the BISCR Register address 0x0016. For
proper operation in Analog Loopback mode, attach 100Ω terminations to the RJ45 connector. External
Loopback can be performed while working in normal mode (Bits 3:0 of the BISCR register are asserted to
0, and on the RJ45 connector, pin 1 is connected to pin 3 and pin 2 is connected to pin 6). To maintain
the desired operating mode, Auto-Negotiation should be disabled before selecting Loopback mode. This
constraint does not apply for external-loopback mode. For selected loopback Delay propagation timing
please see Section 9.10.21.
3.9.2 Far-End Loopback
Far-end (Reverse) loopback is a special test mode to allow testing the PHY from the link-partner side. In
this mode, data that is received from the link partner passes through the PHY's receiver, looped back on
the MII and transmitted back to the link partner. Figure 3-6 shows Far-end loopback functionality.
MAC/
Switch
M
I
PCS
I
Signal
Process
PHY Digital
PHY
AFE
XFMR _{CAT5 Cable}
&
Link Partner
RJ45
Reverse Loopback
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Figure 3-6. Block Diagram, Far-End Loopback Mode
The Reverse Loopback mode is selected by setting bit 4 in the BIST Control Register (BISCR), MII
register address 0x0016.
While in Reverse Loopback mode the data is looped back and also transmitted onto the MAC Interface
and all data signals that come from the MAC are ignored.
Table 3-6 describes the operating modes for Far-End Loopback.
Table 3-6. Far-End Loopback Modes
OPERATIONAL MAC
INT.
Operational Setting
MII MODE
Force/ANEG 10/100
RMII MODE
Force/ANEG 10
14
Hardware Configuration
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