TLK105_16 Datasheet, PDF (70/104 Pages) Texas Instruments – TLK105 TLK106 Industrial Temp, Single Port 10/100Mbs Ethernet Physical Layer

TLK105
TLK106
SLLSEB8C – AUGUST 2012 – REVISED APRIL 2016
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Table 8-33. TX_CLK Phase Shift Register (TXCPSR), address 0x0042 (continued)
BIT BIT NAME
3:0 Phase Shift
Value
DEFAULT
0000,RW
DESCRIPTION
TX Clock Phase Shift Value:
The value of this register represents the current phase shift between Reference clock at XI and MII
Transmit Clock at TX_CLK. Any different value that will be written to these bits will shift TX_CLK by 4
times the difference (in nSec).
For example, if the value of this register is 0x2, Writing 0x9 to this register shifts TX_CLK by 28nS (4
times 7).However, since the maximum difference between XI and TX_CLK could be 40nSec (value of
10) in case of writing value bigger than 10, the updated value is the written value modulo 10.
8.6 Power Back Off Control Register (PWRBOCR)
Table 8-34. Power Back Off Control Register (PWRBOCR), address 0x00AE
BIT BIT NAME
15 RESERVED
14 RESERVED
13:9 RESERVED
8:6 Power Back
Off
5:0 RESERVED
DEFAULT
1, RO
0, RO
00 000, RO
0, RW
10 0000, RO
DESCRIPTION
RESERVED
RESERVED
RESERVED
Power Back Off Level: See Application Note SLLA328
000 = Normal Operation
001 = Level 1 (up to 140m cable between TLK link partners)
010 = Level 2 (up to 100m cable between TLK link partners)
011 = Level 3 (up to 80m cable between TLK link partners)
Others = Reserved
RESERVED
8.7 Voltage Regulator Control Register (VRCR)
This register gives the host processor the ability to power down the voltage-regulator block of the PHY via
register access. This power-down operation is available in systems operating with an external power
supply.
Table 8-35. Voltage Regulator Control Register (VRCR), address 0x00D0
BIT BIT NAME
15 VRPD
14:0 RESERVED
DEFAULT
DESCRIPTION
0, RW, SC
Voltage Regulator Power Down:
1 = Power Down. Allow the system to power down the voltage regulator block of the PHY
using register access.
0 = Normal Operation. Voltage Regulator is powered and outputs voltage on the PFBOUT
pin.
000 0000 0000, RW RESERVED: Must be written as 0.
8.8 Cable Diagnostic Configuration/Result Registers
8.8.1 ALCD Control and Results 1 (ALCDRR1)
Table 8-36. ALCD Control and Results 1 (ALCDRR1), address 0x0155
BIT
BIT NAME
15 alcd_start
14:13
12 alcd_done
11:4 alcd_out1
3 RESERVED
2:0 alcd_ctrl
DEFAULT
0, SC
00, RO
0, RO
0000 0000,
RO
0, RO
001,RW
DESCRIPTION
1 = Start ALCD
RESERVED: Writes ignored, read as 0.
TPTD Diagnostic Bypass
1 = Bypass TPTD diagnostic. TDR on TPTD pair is not executed.
0 = TDR is executed on TPTD pair
alcd_out1
RESERVED: Writes ignored, read as 0
Control of ALCD Average factor
70
Register Block
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