TLK105_16 Datasheet, PDF (65/104 Pages) Texas Instruments – TLK105 TLK106 Industrial Temp, Single Port 10/100Mbs Ethernet Physical Layer

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TLK105
TLK106
SLLSEB8C – AUGUST 2012 – REVISED APRIL 2016
8.1.22 LED Control Register (LEDCR)
This register provides the ability to directly manually control the Link LED output.
Table 8-26. LED Control Register (LEDCR), address 0x0018
BIT NAME
15:11 RESERVED
10:9 Blink Rate
8 RESERVED
7 LED Link Polarity
6 RESERVED
5 RESERVED
4 Drive Link LED
3 RESERVED
2 RESERVED
1 Link LED On/Off Setting
0 RESERVED
DEFAULT
0000 0, ro
10, RW
RO
0, RW,
Pin_Strap
RO
RO
0, RW
RO
RO
0, RW
RO
DESCRIPTION
RESERVED: Writes ignored, read as 0.
LED Blinking Rate (ON/OFF duration):
00 = 20Hz (50mSec)
01 = 10Hz (100mSec)
10 = 5Hz (200mSec)
11 = 2Hz (500mSec)
RESERVED
LED Link Polarity Setting:
1 = Active High polarity setting
0 = Active Low polarity setting
The Link LED polarity is defined by the strap value of this pin. If the pin is
strapped high via a pull-up resistor, the LED will be active low. If the pin is
strapped low via a pull-down resistor, the LED will be active high. This register
allows override of the strapping value.
RESERVED
RESERVED
Drive LED Link to the forced On/Off setting defined in bit 1:
1 = Drive value of On/Off bit onto LED_LINK output pin
0 = Normal operation
RESERVED
RESERVED
Value to force on Link LED output
RESERVED
8.1.23 PHY Control Register (PHYCR)
This register provides the ability to control and set general functionality inside the PHY.
Table 8-27. PHY Control Register (PHYCR), address 0x0019
BIT NAME
15 Auto MDI/X
Enable
DEFAULT
1, RW,
Pin_Strap
14 Force MDI/X 0, RW
13 Pause RX
Status
0, RO
12 Pause TX
Status
0,RO
11 MI Link
Status
0, RO
10:8 RESERVED
7
Bypass LED
Stretching
000, RO
0, RW
6
RESERVED RO
DESCRIPTION
Auto-MDIX Enable:
1 = Enable Auto-negotiation Auto-MDIX capability
0 = Disable Auto- negotiation Auto-MDIX capability
Force MDIX:
1 = Force MDI pairs to cross. (Receive on TPTD pair, Transmit on TPRD pair)
0 = Normal operation. (Transmit on TPTD pair, Receive on TPRD pair)
Pause Receive Negotiated Status: Indicates that pause receive should be enabled in the MAC.
Based on bits [11:10] in ANAR register and bits [11:10] in ANLPAR register settings.
This function shall be enabled according to IEEE 802.3 Annex 28B Table 28B-3, “Pause
Resolution”, only if the Auto-Negotiated Highest Common Denominator is a full duplex technology.
Pause Transmit Negotiated Status:
Indicates that pause transmit should be enabled in the MAC. Based on bits [11:10] in ANAR register
and bits [11:10] in ANLPAR register settings.
This function shall be enabled according to IEEE 802.3 Annex 28B Table 28B-3, “Pause
Resolution”, only if the Auto-Negotiated Highest Common Denominator is a full duplex technology.
MII Link Status:
1 = 100BT Full-duplex Link is active and it was established using Auto-Negotiation
0 = No active link of 100BT Full-duplex, established using Auto-Negotiation
RESERVED: Writes ignored, read as 0.
Bypass LED Stretching:
1 = Bypass LED stretching
0 = Normal LED operation
Set this bit to 1 to bypass the LED stretching; the LED reflects the internal value.
RESERVED
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