SM320VC5510A-EP Datasheet, PDF (9/82 Pages) Texas Instruments – SM320VC5510A-EP Fixed-Point Digital Signal Processor

1 Features
D Controlled Baseline
− One Assembly/Test Site, One Fabrication
Site
D Extended Temperature Performance of
−40°C to 85°C
D Enhanced Diminishing Manufacturing
Sources (DMS) Support
D Enhanced Product-Change Notification
D Qualification Pedigree^†
D High-Performance, Low-Power,
Fixed-Point 320C55x
Digital Signal Processor (DSP)
− 5-ns Instruction Cycle Time
− 200-MHz Clock Rate
− One/Two Instructions Executed per Cycle
− Dual Multipliers (Up to 400 Million
Multiply-Accumulates Per Second
(MMACS))
− Two Arithmetic/Logic Units
− One Internal Program Bus
− Three Internal Data/Operand Read Buses
− Two Internal Data/Operand Write Buses
D Instruction Cache (24K Bytes)
D 160K x 16-Bit On-Chip RAM Composed of:
− Eight Blocks of 4K × 16-Bit
Dual-Access RAM (DARAM) (64K Bytes)
− 32 Blocks of 4K × 16-Bit
Single-Access RAM (SARAM)
(256K Bytes)
D 16K × 16-Bit On-Chip ROM (32K Bytes)
Features
D 8M × 16-Bit Maximum Addressable
External Memory Space
D 32-Bit External Memory Interface (EMIF)
With Glueless Interface to:
− Asynchronous Static RAM (SRAM)
− Asynchronous EPROM
− Synchronous DRAM (SDRAM)
− Synchronous Burst SRAM (SBSRAM)
D Programmable Low-Power Control of Six
Device Functional Domains
D On-Chip Peripherals
− Two 20-Bit Timers
− Six-Channel Direct Memory Access
(DMA) Controller
− Three Multichannel Buffered Serial Ports
(McBSPs)
− 16-Bit Parallel Enhanced Host-Port
Interface (EHPI)
− Programmable Digital Phase-Locked
Loop (DPLL) Clock Generator
− Eight General-Purpose I/O (GPIO) Pins
and Dedicated General-Purpose
Output (XF)
D On-Chip Scan-Based Emulation Logic
D IEEE Std 1149.1^‡ (JTAG) Boundary Scan
Logic
D 240-Terminal MicroStar BGA
(Ball Grid Array) (GGW Suffix)
D 3.3-V I/O Supply Voltage
D 1.6-V Core Supply Voltage^§
TMS320C55x and MicroStar BGA are trademarks of Texas Instruments.
Other trademarks are the property of their respective owners.
† _{Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range.}
This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST,
electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this
component beyond specified performance and environmental limits.
‡ _{IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.}
§ _{Some TMX320VC5510 prototype devices may require core supply voltage other than 1.6 V. See the Electrical Specification section of this data}
manual for more information. See the TMS320VC5510 Digital Signal Processor Silicon Errata (literature number SPRZ008) for further
clarification and distinguishing markings.
August 2003 − Revised November 2003
SGUS045A
1