SM320VC5510A-EP Datasheet, PDF (14/82 Pages) Texas Instruments – SM320VC5510A-EP Fixed-Point Digital Signal Processor

Introduction
2.3 Signal Descriptions
Table 2−2 lists each signal, function, and operating mode(s) grouped by function. See Section 2.2 for exact
pin locations based on package type.
Table 2−2. Signal Descriptions
SIGNAL
NAME
TYPE† OTHER‡
DESCRIPTION
EMIF - ADDRESS BUS
A[21:0]
External memory address bus (byte address). Address all external memory (program and
O/Z
E,F
data). Since A[23:22] are redundant to the CE[3:0] memory space selects in terms of memory
addressing capability, A[23:22] are not externally provided.
EMIF - CONTROL SIGNALS COMMON TO ALL MEMORY TYPES
CE0
CE1
CE2
O/Z
E,F
External memory space enables. Select one of four external memory ranges based on the
address.
CE3
BE0
Byte-enable control. Can be used as chip selects for external memory. These signals respond
BE1
BE2
O/Z
E,F
according to the data width of the memory access. 8-bit accesses cause a single byte enable to
respond. 16-bit accesses cause two byte enables to respond. 32-bit accesses cause all four byte
BE3
enables to respond.
CLKMEM
O/Z
E,F
Memory interface clock (for SDRAM / SBSRAM). Clock for synchronizing the external
synchronous memories to the C55x external memory interface.
EMIF - DATA BUS
D[31:0]
I/O/Z
D,E,F
External data bus. Provides data exchange between external memories and the C55x external
memory interface.
The bus holders on D[31:0] are controlled by the BH bit in the system register (SYSR).
EMIF - BUS ARBITRATION
HOLD
I
−
Hold request. HOLD is asserted by an external host to request control of the address, data and
control signals.
HOLDA
O/Z
Hold acknowledge. HOLDA is asserted by the DSP to indicate that the DSP is in the HOLD state
F
and that the EMIF address, data and control signals are in a high-impedance state, allowing the
external memory interface to be accessed by other devices.
EMIF - ASYNCHRONOUS MEMORY CONTROL SIGNALS
ARE
Asynchronous memory read enable. ARE acts as a strobe during asynchronous memory reads
only.
AOE
Asynchronous memory output enable. AOE indicates whether a memory access is a read
O/Z
E,F
(low) or a write (high).
AWE
Asynchronous memory write enable. AWE acts as a strobe during asynchronous memory
writes only.
ARDY
I
Asynchronous memory ready input. ARDY indicates that an external device is ready for a bus
transaction to be completed. If the device is not ready (ARDY is low), the processor extends the
memory access by one cycle and checks ARDY again. The ARDY signal is sampled at the end
of the STROBE period in the memory access.
† _{I = Input, O = Output, S = Supply, Z = High impedance}
‡ _{Other Pin Characteristics:}
A − Internal pullup (always enabled)
E − Pin is high impedance in HOLD mode (due to HOLD pin).
B − Internal pulldown (always enabled)
F − Pin is high impedance in OFF mode (due to EMU1/OFF pin).
C − Hysteresis input
G − Pin can be configured as a general-purpose input.
D − Pin has bus holder
H − PIn can be configured as a general-purpose output.
J − Internal pullup enabled by the HPE bit in the system register (SYSR)
K − Internal pulldown enabled by the HPE bit in the system register (SYSR)
6
SGUS045A
August 2003 − Revised November 2003