SM320VC5510A-EP Datasheet, PDF (74/82 Pages) Texas Instruments – SM320VC5510A-EP Fixed-Point Digital Signal Processor

Electrical Specifications
5.15 Enhanced Host-Port Interface (EHPI) Timing
Table 5−35 and Table 5−36 assume testing over recommended operating conditions (see Figure 5−28
through Figure 5−32).
Table 5−35. EHPI Timing Requirements
NO.
E11 tsu(HASL-HDSL)
Setup time, HAS low before HDS low
E12 th(HDSL-HASL)
Hold time, HAS low after HDS low
E13
tsu(HCNTLV-HDSL)
Setup time, (HR/W, HA[19:0],
HCNTL[1:0]) valid before HDS low
E14 th(HDSL-HCNTLIV) Hold time, (HR/W, HA[19:0], HCNTL[1:0]) invalid after HDS low
E15 tw(HDSL)
Pulse duration, HDS low
E16 tw(HDSH)
Pulse duration, HDS high
E17 tsu(HDV-HDSH)
Setup time, HD bus write data valid before HDS high
E18 th(HDSH-HDIV)
Hold time, HD bus write data invalid after HDS high
E19 tsu(HCNTLV-HASL) Setup time, (HR/W, HCNTL[1:0]) valid before HAS low
E20 th(HASL-HCNTLIV) Hold time, (HR/W, HCNTL[1:0]) valid after HAS low
† _{P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.}
VC5510-200
MIN MAX
4
3
UNIT
ns
ns
4
ns
4
ns
4P†
ns
4P†
ns
5
ns
3
ns
5
ns
3
ns
Table 5−36. EHPI Switching Characteristics
NO.
E1 td(HDSL-HDD)M
E2 td(HDSL-HDV1)M
PARAMETER
Delay time, HDS low to HD bus read data driven
(memory access)
Delay time, HDS low to HD bus read data valid
(memory access)
VC5510-200
UNIT
MIN
MAX
6
16 ns
14P+10†‡
ns
E4 td(HDSL-HDD)R
Delay time, HDS low to HD bus read data driven
(register access)
6
16 ns
E5 td(HDSL-HDV)R
Delay time, HDS low to HD bus read data valid
(register access)
16 ns
E6 tdis(HDSH-HDIV)
E7 td(HDSL-HRDYL)
Disable time, HDS high to HD bus read data invalid
Delay time, HDS low to HRDY low (during reads)
6
16 ns
P+10† ns
E8 td(HDV-HRDYH)
Delay time, HD bus valid to HRDY high (during reads)
2
ns
E9 td(HDSH-HRDYL)
Delay time, HDS high to HRDY low (during writes)
16 ns
E10 td(HDSH-HRDYH)
Delay time, HDS high to HRDY high (during writes)
14P+10†
ns
† _{P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.}
‡ _{EHPI latency is dependent on the number of DMA channels active, their priorities and their source/destination ports. The latency shown assumes}
no competing CPU or DMA activity to the memory resource being accessed by the EHPI.
66 SGUS045A
August 2003 − Revised November 2003