SM320VC5510A-EP Datasheet, PDF (65/82 Pages) Texas Instruments – SM320VC5510A-EP Fixed-Point Digital Signal Processor

Electrical Specifications
5.13 TIN/TOUT Timings
Table 5−21 and Table 5−22 assumes testing over recommended operating conditions (see Figure 5−19 and
Figure 5−20).
Table 5−21. TIN/TOUT Pins Configured as Inputs Timing Requirements^†
VC5510-200
NO.
UNIT
MIN
MAX
T4 tw(TIN/TOUTL)
Pulse width, TIN/TOUT low
T5 tw(TIN/TOUTH)
Pulse width, TIN/TOUT high
† _{P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.}
2P + 1
ns
2P + 1
ns
Table 5−22. TIN/TOUT Pins Configured as Outputs Switching Characteristics^†‡
NO.
PARAMETER
VC5510-200
MIN MAX
T1 td(COH-TIN/TOUTH)
Delay time, CLKOUT high to TIN/TOUT high
0
2
T2 td(COH-TIN/TOUTL)
Delay time, CLKOUT high to TIN/TOUT low
0
2
T3 tw(TIN/TOUT)
Pulse duration, TIN/TOUT (output)
P
† _{P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.}
‡ _{For proper operation of the TIN/TOUT pin configured as an output, the timer period must be configured for at least 4 cycles.}
UNIT
ns
ns
ns
TIN/TOUT
as Input
T5
T4
Figure 5−19. TIN/TOUT Timing When Configured as Inputs
CLKOUT
TIN/TOUT
as Output
T1
T2
T3
Figure 5−20. TIN/TOUT Timing When Configured as Outputs
August 2003 − Revised November 2003
SGUS045A
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