SM320VC5510A-EP Datasheet, PDF (51/82 Pages) Texas Instruments – SM320VC5510A-EP Fixed-Point Digital Signal Processor

Electrical Specifications
5.6.2 Clock Generation in Lock Mode (DPLL Synthesis Enabled)
The frequency of the reference clock provided at the CLKIN pin can be multiplied by a synthesis factor of N
to generate the internal CPU clock cycle. The synthesis factor is determined by:
N
+
M
D_L
where: M = the multiply factor set in the PLL_MULT field of the clock mode register,
D_L = the divide factor set in the PLL_DIV field of the clock mode register
Valid values for M are (multiply by) 2 to 31. Valid values for D_L are (divide by) 1, 2, 3, and 4.
For detailed information on clock generation configuration, see the TMS320C55x DSP Peripherals Reference
Guide (literature number SPRU317).
Table 5−5 and Table 5−6 assume testing over recommended operating conditions and H = 0.5t_c(CO) (see
Figure 5−3).
Table 5−5. CLKIN in Lock Mode Timing Requirements
NO.
C7 tc(CI)
C8 tf(CI)
C9 tr(CI)
Cycle time, CLKIN
Fall time, CLKIN
Rise time, CLKIN
DPLL synthesis enabled
VC5510-200
MIN MAX
20† 400
6
6
UNIT
ns
ns
ns
C10 tw(CIL) Pulse duration, CLKIN low
4
ns
C11 tw(CIH) Pulse duration, CLKIN high
4
ns
† _{The clock frequency synthesis factor and minimum CLKIN cycle time should be chosen such that the resulting CLKOUT cycle time is within the}
specified range (tc(CO)).
Table 5−6. CLKOUT in Lock Mode Switching Characteristics
NO.
PARAMETER
C1 tc(CO)
Cycle time, CLKOUT
C2 td(CI-CO)
Delay time, CLKIN high/low to CLKOUT high/low
C3 tf(CO)
Fall time, CLKOUT
C4 tr(CO)
Rise time, CLKOUT
C5 tw(COL)
Pulse duration, CLKOUT low
C6 tw(COH)
Pulse duration, CLKOUT high
‡ _{N = Clock frequency synthesis factor}
C10
C7
C11
VC5510-200
MIN
5
1
TYP
tc(CI)/N‡
7
MAX
14
1
1
H−1
H+1
H−1
H+1
UNIT
ns
ns
ns
ns
ns
ns
C8
C9
CLKIN
C2
C1
C3
C5
C6
C4
CLKOUT
Bypass Mode
NOTE A: The waveform relationship of CLKIN to CLKOUT depends on the multiply and divide factors chosen. The waveform relationship shown
in Figure 5−3 is intended to illustrate the timing parameters only and may differ based on configuration.
Figure 5−3. External Multiply-by-N Clock Timing
August 2003 − Revised November 2003
SGUS045A
43