SM320VC5510A-EP Datasheet, PDF (66/82 Pages) Texas Instruments – SM320VC5510A-EP Fixed-Point Digital Signal Processor

Electrical Specifications
5.14 Multichannel Buffered Serial Port (McBSP) Timings
5.14.1 McBSP Transmit and Receive Timings
Table 5−23 and Table 5−24 assume testing over recommended operating conditions (see Figure 5−21 and
Figure 5−22).
Table 5−23. McBSP Timing Requirements^†‡
VC5510-200
NO.
UNIT
MIN MAX
M11 tc(CKRX)
M12 tw(CKRX)
M13 tr(CKRX)
M14 tf(CKRX)
M15 tsu(FRH-CKRL)
Cycle time, CLKR/X
Pulse duration, CLKR/X high or CLKR/X low
Rise time, CLKR/X
Fall time, CLKR/X
Setup time, external FSR high before CLKR low
CLKR/X ext
2P
ns
CLKR/X ext
P−1
ns
CLKR/X ext
5 ns
CLKR/X ext
5 ns
CLKR int
5
ns
CLKR ext
1
M16 th(CKRL-FRH)
Hold time, external FSR high after CLKR low
CLKR int
0
ns
CLKR ext
2
M17 tsu(DRV-CKRL)
Setup time, DR valid before CLKR low
CLKR int
4
ns
CLKR ext
1
M18 th(CKRL-DRV)
Hold time, DR valid after CLKR low
CLKR int
0
ns
CLKR ext
2
M19 tsu(FXH-CKXL)
Setup time, external FSX high before CLKX low
CLKX int
5
ns
CLKX ext
1
M20 th(CKXL-FXH)
Hold time, external FSX high after CLKX low
CLKX int
0
ns
CLKX ext
2
† _{Polarity bits CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that signal are}
also inverted.
‡ _{P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.}
58 SGUS045A
August 2003 − Revised November 2003