SM320VC5510A-EP Datasheet, PDF (16/82 Pages) Texas Instruments – SM320VC5510A-EP Fixed-Point Digital Signal Processor

Introduction
Table 2−2. Signal Descriptions (Continued)
SIGNAL
NAME
HA[19:3]
HA2/HAS
HA1/HCNTL1
HA0
HD[15:0]
HCS
HA2/HAS
HR/W
HDS1
HDS2
HRDY
TYPE† OTHER‡
DESCRIPTION
ENHANCED HOST-PORT INTERFACE (EHPI)
Host address bus:
In non-multiplexed mode (HMODE pin high):
HA[19:0] functions as the host address bus only
In multiplexed mode (HMODE pin low):
I
J
HA[19:3] are disabled
HA2/HAS functions as HAS (Host Address Strobe). Hosts with multiplexed address and data pins
may require HAS to latch the address in the HPIA register.
HA1/HCNTL1 functions as HCNTL1 (Host Control Input) and with HCNTL0 determines the type
of transaction being performed.
Host data bus. Provides data exchange between the host and C55x EHPI.
I/O/Z
ËËËËË _I
ËËËËËËËËËËËËËËË _I
D,F
The bus holders on HD[15:0] are controlled by the HBH bit in the system register (SYSR).
J
Host chip select. HCS is the select input for the EHPI and must be driven low during accesses.
If the EHPI is not used, HCS must be driven high.
J
Host address strobe. Operates as HAS when HMODE is low (multiplexed mode). Hosts with
multiplexed address and data pins may require HAS to latch the address in the HPIA register.
I
J
Host read or write select. Controls the direction of the EHPI transfer.
I
J
Host data strobes. HDS1 and HDS2 are driven by the host read and write strobes to control data
transfers.
O/Z
F,J
Host ready (from DSP to host). HRDY informs the host when the EHPI is ready for the next
transfer.
HBE0
EHPI byte enables. HBE0 and HBE1 are driven low selectively by the host to indicate whether
the transaction involves the lower byte only, the upper byte only, or both.
I
K
As of revision 2.1, the byte-enable function on the EHPI will no longer be supported. These pins
HBE1
must be driven low by an external device, by external pulldown resistors or by the internal
pulldown circuit controlled by the HPE bit in the SYSR register.
HMODE
I
J
Host multiplexed/non-multiplexed mode select. When HMODE is high, the EHPI operates in
nonmultiplexed mode. When HMODE is low, the EHPI operates in multiplexed mode.
HCNTL0
I
HA1/HCNTL1
J
Host control selects. HCNTL0 and HCNTL1 select host accesses to EHPI address, data or
control registers. HA1/HCNTL operates as HCNTL when HMODE is low (multiplexed mode).
HINT
O/Z
F
Host interrupt (from DSP to host). This output is used to interrupt the host. HINT is high
following reset.
† _{I = Input, O = Output, S = Supply, Z = High impedance}
‡ _{Other Pin Characteristics:}
A − Internal pullup (always enabled)
E − Pin is high impedance in HOLD mode (due to HOLD pin).
B − Internal pulldown (always enabled)
F − Pin is high impedance in OFF mode (due to EMU1/OFF pin).
C − Hysteresis input
G − Pin can be configured as a general-purpose input.
D − Pin has bus holder
H − PIn can be configured as a general-purpose output.
J − Internal pullup enabled by the HPE bit in the system register (SYSR)
K − Internal pulldown enabled by the HPE bit in the system register (SYSR)
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SGUS045A
August 2003 − Revised November 2003