SM320VC5510A-EP Datasheet, PDF (61/82 Pages) Texas Instruments – SM320VC5510A-EP Fixed-Point Digital Signal Processor

Electrical Specifications
5.8 HOLD and HOLDA Timings
Table 5−13 and Table 5−14 assume testing over recommended operating conditions (see Figure 5−14).
Table 5−13. HOLD and HOLDA Timing Requirements
VC5510-200
NO.
MIN MAX
H1 tsu(HOLDH-COH)
Setup time, HOLD high before CLKOUT high†
7
† _{HOLD is synchronized internally. If the setup time shown is not met, HOLD will be recognized on the next clock cycle.}
UNIT
ns
Table 5−14. HOLD and HOLDA Switching Characteristics^‡
VC5510-200
NO.
PARAMETER
UNIT
MIN MAX
H2 tR(COH-BHZ)
Response time, CLKOUT high to EMIF Bus high impedance (HZ)¶
4P
§ _ns
H3 tR(COH-HOLDAL) Response time, CLKOUT high to HOLDA low
5P−1
ns
H4 tR(COH-HOLDAH) Response time, CLKOUT high to HOLDA high
H5 tR(COH-BLZ)
Response time, CLKOUT high to EMIF Bus low impedance (LZ) (active)¶
4P−1 4P+5 ns
4P−1 4P+5 ns
‡ _{P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.}
§ _{All pending EMIF transactions are allowed to complete before HOLDA is asserted. If no bus transactions are occurring, then the minimum delay}
time can be achieved. Also, bus hold can be indefinitely delayed by setting NOHOLD = 1.
¶ _{EMIF Bus consists of CE[3:0], BE[3:0], D[31:0], A[21:0], ARE, AOE, AWE, SSADS, SSOE, SSWE, CLKMEM, SDA10, SDRAS, SDCAS, and}
SDWE.
CLKOUT
HOLD
HOLDA
EMIF BUS†
H1
H3
H2
H1
H4
H5
† _{EMIF Bus consists of CE[3:0], BE[3:0], D[31:0], A[21:0], ARE, AOE, AWE, SSADS, SSOE, SSWE, SDA10, SDRAS, SDCAS, SDWE, and}
CLKMEM.
Figure 5−14. HOLD/HOLDA Timing
August 2003 − Revised November 2003
SGUS045A
53