SM320VC5510A-EP Datasheet, PDF (57/82 Pages) Texas Instruments – SM320VC5510A-EP Fixed-Point Digital Signal Processor

Electrical Specifications
5.7.3 Synchronous DRAM (SDRAM) Timing
Table 5−11 and Table 5−12 assume testing over recommended operating conditions (see Figure 5−8 through
Figure 5−13).
Table 5−11. Synchronous DRAM Cycle Timing Requirements
NO.
SD7 tsu(DV-CLKMEMH)
SD8 th(CLKMEMH-DV)
Setup time, read data valid before CLKMEM high
Hold time, read data valid after CLKMEM high
VC5510-200
MIN MAX
5
2
UNIT
ns
ns
Table 5−12. Synchronous DRAM Cycle Switching Characteristics
NO.
SD1
SD2
SD3
SD4
SD5
SD6
SD9
SD10
SD11
SD12
SD13
SD14
SD15
SD16
SD17
SD18
td(CLKMEMH-CEL)
td(CLKMEMH-CEH)
td(CLKMEMH-BEV)
td(CLKMEMH-BEIV)
td(CLKMEMH-AV)
td(CLKMEMH-AIV)
td(CLKMEMH-SDCASL)
td(CLKMEMH-SDCASH)
td(CLKMEMH-DV)
td(CLKMEMH-DIV)
td(CLKMEMH-SDWEL)
td(CLKMEMH-SDWEH)
td(CLKMEMH-SDA10V)
td(CLKMEMH-SDA10IV)
td(CLKMEMH-SDRASL)
td(CLKMEMH-SDRASH)
PARAMETER
Delay time, CLKMEM high to CEx low
Delay time, CLKMEM high to CEx high
Delay time, CLKMEM high to BEx valid
Delay time, CLKMEM high to BEx invalid
Delay time, CLKMEM high to address valid
Delay time, CLKMEM high to address invalid
Delay time, CLKMEM high to SDCAS low
Delay time, CLKMEM high to SDCAS high
Delay time, CLKMEM high to data valid
Delay time, CLKMEM high to data invalid
Delay time, CLKMEM high to SDWE low
Delay time, CLKMEM high to SDWE high
Delay time, CLKMEM high to SDA10 valid
Delay time, CLKMEM high to SDA10 invalid
Delay time, CLKMEM high to SDRAS low
Delay time, CLKMEM high to SDRAS high
VC5510-200
MIN MAX
3
6
3
6
3
6
3
6
3
6
3
6
3
5
3
5
3
5
3
5
3
5
3
5
3
5
3
5
3
5
3
5
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
August 2003 − Revised November 2003
SGUS045A
49