SM320VC5510A-EP Datasheet, PDF (28/82 Pages) Texas Instruments – SM320VC5510A-EP Fixed-Point Digital Signal Processor

Functional Overview
3.2.4 General-Purpose Input/Output Port (GPIO)
The 5510 provides eight dedicated general-purpose input/output pins, IO0−IO7. Each pin can be
independently configured as an input or an output using the I/O Direction Register (IODIR). The I/O Data
Register (IODATA) is used to monitor the logic state of pins configured as inputs and control the logic state
of pins configured as outputs. IODIR and IODATA are accessible to the CPU and to the DMA controller at
addresses in I/O space. See Table 3−19 for address information. The description of the IODIR is shown in
Figure 3−5 and Table 3−7. The description of IODATA is shown in Figure 3−6 and Table 3−8.
To configure a GPIO pin as an input, clear the direction bit that corresponds to the pin in IODIR to 0. To read
the logic state of the input pin, read the corresponding bit in IODATA.
To configure a GPIO pin as an output, set the direction bit that corresponds to the pin in IODIR to 1. To control
the logic state of the output pin, write to the corresponding bit in IODATA.
15
8
7
6
Reserved
IO7DIR IO6DIR
R−00000000
R/W−0
R/W−0
LEGEND: R = Read, W = Write, n = value after reset
5
IO5DIR
R/W−0
4
IO4DIR
R/W−0
3
IO3DIR
R/W−0
2
IO2DIR
R/W−0
Figure 3−5. I/O Direction Register (IODIR) Bit Layout
1
IO1DIR
R/W−0
0
IO0DIR
R/W−0
BIT
NO.
15−8
BIT
NAME
Reserved
7−0
IOxDIR
Table 3−7. I/O Direction Register (IODIR) Bit Functions
RESET
VALUE
FUNCTION
0
These bits are reserved and are unaffected by writes.
IOx Direction Control Bit. Controls whether IOx operates as an input or an output.
0
IOxDIR = 0 IOx is configured as an input.
IOxDIR = 1 IOx is configured as an output.
15
8
7
6
5
4
3
2
Reserved
IO7D
IO6D
IO5D
IO4D
IO3D
IO2D
R−00000000
R/W−pin R/W−pin R/W−pin R/W−pin R/W−pin R/W−pin
LEGEND: R = Read, W = Write, pin = value present on the pin (IO7−IO0 default to inputs after reset)
1
IO1D
R/W−pin
0
IO0D
R/W−pin
Figure 3−6. I/O Data Register (IODATA) Bit Layout
Table 3−8. I/O Data Register (IODATA) Bit Functions
BIT
BIT
RESET
NO.
NAME
VALUE
FUNCTION
15−8 Reserved
0
These bits are reserved and are unaffected by writes.
7−0
IOxD
IOx Data Bit.
If IOx is configured as an input (IOxDIR = 0 in IODIR):
IOxD = 0
The signal on the IOx pin is low.
pin†
IOxD = 1
The signal on the IOx pin is high.
If IOx is configured as an output (IOxDIR = 1 in IODIR):
IOxD = 0
Drive the signal on the IOx pin low.
IOxD = 1
Drive the signal on the IOx pin high.
† _{pin = value present on the pin (IO7−IO0 default to inputs after reset)}
20 SGUS045A
August 2003 − Revised November 2003