SM320VC5510A-EP Datasheet, PDF (67/82 Pages) Texas Instruments – SM320VC5510A-EP Fixed-Point Digital Signal Processor

Electrical Specifications
Table 5−24. McBSP Switching Characteristics^†‡
NO.
PARAMETER
VC5510-200
UNIT
MIN MAX
M1 tc(CKRX)
M2 tw(CKRXH)
M3 tw(CKRXL)
M4 td(CKRH-FRV)
Cycle time, CLKR/X
Pulse duration, CLKR/X high
Pulse duration, CLKR/X low
Delay time, CLKR high to internal FSR valid
CLKR/X int
2P
ns
CLKR/X int D−1§ D+1§ ns
CLKR/X int C−1§ C+1§ ns
CLKR int
−2
2 ns
CLKR ext
3
7 ns
M5 td(CKXH-FXV)
Delay time, CLKX high to internal FSX valid
CLKX int
CLKX ext
−2
2
ns
3
7
M6 tdis(CKXH-DXHZ)
Disable time, CLKX high to DX high impedance
following last data bit
CLKX int
CLKX ext
0
2
ns
1
11
Delay time, CLKX high to DX valid.
CLKX int
6
This applies to all bits except the first bit transmitted.
CLKX ext
9
M7 td(CKXH-DXV)
Delay time, CLKX high to DX valid¶
CLKX int
DXENA = 0
CLKX ext
6
9 ^ns
CLKX int
Only applies to first bit transmitted when in Data _{DXENA = 1}
Delay 1 or 2 (XDATDLY=01b or 10b) modes
CLKX ext
2P+6
2P+9
CLKX int
0
Enable time, CLKX high to DX driven¶
DXENA = 0
CLKX ext
6
M8 ten(CKXH-DX)
ns
CLKX int
P
Only applies to first bit transmitted when in Data _{DXENA = 1}
Delay 1 or 2 (XDATDLY=01b or 10b) modes
CLKX ext
P+6
M9 td(FXH-DXV)
Delay time, FSX high to DX valid¶
DXENA = 0
Only applies to first bit transmitted when in Data _{DXENA = 1}
Delay 0 (XDATDLY=00b) mode.
FSX int
FSX ext
FSX int
FSX ext
5
9
ns
2P+5
2P+9
Enable time, FSX high to DX driven¶
FSX int
0
DXENA = 0
FSX ext
6
M10 ten(FXH-DX)
ns
FSX int
P
Only applies to first bit transmitted when in Data _{DXENA = 1}
Delay 0 (XDATDLY=00b) mode
FSX ext
P+6
† _{Polarity bits CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that signal are}
also inverted.
‡ _{P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.}
§ _{T=CLKRX period = (1 + CLKGDV) * P}
C=CLKRX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * P when CLKGDV is even
D=CLKRX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) * P when CLKGDV is even
¶ _{See the TMS320C55x DSP Peripherals Reference Guide (literature number SPRU317) for a description of the DX enable (DXENA) and data}
delay features of the McBSP.
August 2003 − Revised November 2003
SGUS045A
59