SM320VC5510A-EP Datasheet, PDF (53/82 Pages) Texas Instruments – SM320VC5510A-EP Fixed-Point Digital Signal Processor

Electrical Specifications
CLKOUT§
CEx¶
BE[3:0]
Setup = 1†
A1
A2
Strobe = 5†
Not ready = 2 Hold = 1† Extended
Hold = 2†‡
A1
A3
A4
A[21:0]
D[31:0]
A8
AOE
A9
ARE
A5
A7
A6
A8
A9
AWE
ARDY^#
A11
A10
A11
A10
† _{Setup, Strobe, Hold, and Extended Hold are programmable in the EMIF. The programmable Hold period is not associated with the activity of}
the HOLD and HOLDA signals.
‡ _{The extended hold time is programmable in the EMIF and is only present when consecutive memory accesses are made to different CEx spaces,}
or are of different types (read/write).
§ _{All timings referenced to CLKOUT assume CLKOUT is the same frequency as the internal CPU clock (divide-by-1 mode).}
¶ _{The chip enable that becomes active depends on the address.}
# _{ARDY is synchronized internally. If the setup time shown is not met, ARDY will be recognized on the next clock cycle.}
Figure 5−4. Asynchronous Memory Read Timing
August 2003 − Revised November 2003
SGUS045A
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