SM320VC5510A-EP Datasheet, PDF (34/82 Pages) Texas Instruments – SM320VC5510A-EP Fixed-Point Digital Signal Processor

Functional Overview
Table 3−13. DMA Configuration Registers (Continued)
PORT ADDRESS
REGISTER NAME
DESCRIPTION
CHANNEL #2 REGISTERS
0x0C40
0x0C41
0x0C42
0x0C43
0x0C44
0x0C45
0x0C46
0x0C47
0x0C48
0x0C49
0x0C4A
DMA_CSDP2
DMA_CCR2
DMA_CICR2
DMA_CSR2
DMA_CSSA_L2
DMA_CSSA_U2
DMA_CDSA_L2
DMA_CDSA_U2
DMA_CEN2
DMA_CFN2
DMA_CFI2/
DMA_CSFI2†
DMA Channel 2 Source / Destination Parameters Register
DMA Channel 2 Control Register
DMA Channel 2 Interrupt Control Register
DMA Channel 2 Status Register
DMA Channel 2 Source Start Address Register (lower bits)
DMA Channel 2 Source Start Address Register (upper bits)
DMA Channel 2 Source Destination Address Register (lower bits)
DMA Channel 2 Source Destination Address Register (upper bits)
DMA Channel 2 Element Number Register
DMA Channel 2 Frame Number Register
DMA Channel 2 Frame Index Register/
DMA Channel 2 Source Frame Index Register†
0x0C4B
DMA_CEI2/
DMA_CSEI2‡
DMA Channel 2 Element Index Register/
DMA Channel 2 Source Element Index Register‡
0x0C4C
0x0C4D
0x0C4E
0x0C4F
DMA_CSAC2
DMA_CDAC2
DMA_CDEI2
DMA_CDFI2
DMA Channel 2 Source Address Counter
DMA Channel 2 Destination Address Counter
DMA Channel 2 Destination Element Index Register
DMA Channel 2 Destination Frame Index Register
CHANNEL #3 REGISTERS
0x0C60
0x0C61
0x0C62
0x0C63
0x0C64
0x0C65
0x0C66
0x0C67
0x0C68
0x0C69
0x0C6A
DMA_CSDP3
DMA_CCR3
DMA_CICR3
DMA_CSR3
DMA_CSSA_L3
DMA_CSSA_U3
DMA_CDSA_L3
DMA_CDSA_U3
DMA_CEN3
DMA_CFN3
DMA_CFI3/
DMA_CSFI3†
DMA Channel 3 Source / Destination Parameters Register
DMA Channel 3 Control Register
DMA Channel 3 Interrupt Control Register
DMA Channel 3 Status Register
DMA Channel 3 Source Start Address Register (lower bits)
DMA Channel 3 Source Start Address Register (upper bits)
DMA Channel 3 Source Destination Address Register (lower bits)
DMA Channel 3 Source Destination Address Register (upper bits)
DMA Channel 3 Element Number Register
DMA Channel 3 Frame Number Register
DMA Channel 3 Frame Index Register/
DMA Channel 3 Source Frame Index Register†
0x0C6B
DMA_CEI3/
DMA_CSEI3‡
DMA Channel 3 Element Index Register/
DMA Channel 3 Source Element Index Register‡
0x0C6C
DMA_CSAC3
DMA Channel 3 Source Address Counter
0x0C6D
DMA_CDAC3
DMA Channel 3 Destination Address Counter
0x0C6E
DMA_CDEI3
DMA Channel 3 Destination Element Index Register
0x0C6F
DMA_CDFI3
DMA Channel 3 Destination Frame Index Register
† _{On revision 1.x, the channel frame index applies to both source and destination and this register behaves as DMA_CFIn. On revision 2.0 and}
later, DMA_CSFIn and DMA_CDFIn provide separate source and destination frame indexing. Revisions 2.0 and later can be programmed
for software compatibility with revisions 1.x through the Software Compatibility Register (DMA_GSCR).
‡ _{On revision 1.x, the channel element index applies to both source and destination and this register behaves as DMA_CEIn. On revision 2.0}
and later, DMA_CSEIn and DMA_CDEIn provide separate source and destination frame indexing. Revisions 2.0 and later can be programmed
for software compatibility with revisions 1.x through the Software Compatibility Register (DMA_GSCR).
26 SGUS045A
August 2003 − Revised November 2003