SM320VC5510A-EP Datasheet, PDF (58/82 Pages) Texas Instruments – SM320VC5510A-EP Fixed-Point Digital Signal Processor

Electrical Specifications
CLKMEM
CEx†
BE[3:0]‡
A[15:2]§
D[31:0]
SDA10
READ
READ
SD1
SD2
SD3
SD5
CA1
SD6
CA2
SD15
SD7
SD8
D1
D2
SD16
SDRAS
SD9
SD10
SDCAS
SDWE
† _{The chip enable that becomes active depends on the address.}
‡ _{All BE[3:0] signals are driven low (active) during reads. Byte manipulation of the read data is performed inside the EMIF. These signals remain}
active until the next access that is not an SDRAM read occurs.
§ _{The number of address signals used depends on the SDRAM size and width.}
Figure 5−8. Two SDRAM Read Commands (Active Row)
CLKMEM
CEx†
BE[3:0]
A[15:2]‡
D[31:0]
SDA10
WRITE
WRITE
SD1
SD3
BE1
SD5
CA1
SD11
D1
SD15
SD4
BE2
SD6
CA2
SD12
D2
SD2
SD16
SDRAS
SD9
SD10
SDCAS
SD13
SD14
SDWE
† _{The chip enable that becomes active depends on the address.}
‡ _{The number of address signals used depends on the SDRAM size and width.}
Figure 5−9. Two SDRAM WRT Commands (Active Row)
50 SGUS045A
August 2003 − Revised November 2003