SM320VC5510A-EP Datasheet, PDF (24/82 Pages) Texas Instruments – SM320VC5510A-EP Fixed-Point Digital Signal Processor

Functional Overview
BOOTM[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Table 3−4. 320VC5510 Boot Configurations
BOOT PROCESS
No boot
Serial SPI EEPROM boot from McBSP0 supporting 24-bit address
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
No boot
Serial SPI EEPROM boot from McBSP0 supporting 16-bit address
Parallel EMIF boot from 8-bit asynchronous memory
Parallel EMIF boot from 16-bit asynchronous memory
Parallel EMIF boot from 32-bit asynchronous memory
EHPI boot
Standard serial boot from McBSP0, 16-bit element length
Standard serial boot from McBSP0, 8-bit element length
EXECUTION START BYTE ADDRESS
AFTER BOOT IS COMPLETE
FFFF00h (reset vector)
Destination specified in the boot table
−
−
−
−
−
−
FFFF00h (reset vector)
Destination specified in the boot table
Destination specified in the boot table
Destination specified in the boot table
Destination specified in the boot table
010000h (on-chip SARAM)
Destination specified in the boot table
Destination specified in the boot table
3.2 Peripherals
The 5510 supports the following peripherals:
• An external memory interface (EMIF)
• A six-channel direct memory access (DMA) controller
• 16-bit parallel Enhanced Host-Port Interface (EHPI)
• A digital phase-locked loop (DPLL) clock generator
• Two timers
• Three multichannel buffered serial ports (McBSPs)
• Eight configurable general-purpose I/O pins
Peripheral information specific to the 5510 peripherals is included in the following sections. For detailed
information on the C55x DSP peripherals, see the following documents:
• TMS320C55x DSP Functional Overview (literature number SPRU312)
• TMS320C55x DSP Peripherals Reference Guide (literature number SPRU317)
16 SGUS045A
August 2003 − Revised November 2003