SM320VC5510A-EP Datasheet, PDF (55/82 Pages) Texas Instruments – SM320VC5510A-EP Fixed-Point Digital Signal Processor

Electrical Specifications
5.7.2 Synchronous-Burst SRAM (SBSRAM) Timing
Table 5−9 and Table 5−10 assume testing over recommended operating conditions (see Figure 5−6 and
Figure 5−7).
Table 5−9. Synchronous-Burst SRAM Cycle Timing Requirements
VC5510-200
NO.
UNIT
MIN MAX
SB7 tsu(DV-CLKMEMH)
SB8 th(CLKMEMH-DV)
Setup time, read data valid before CLKMEM high
Hold time, read data valid after CLKMEM high
5
ns
2
ns
Table 5−10. Synchronous-Burst SRAM Cycle Switching Characteristics
NO.
PARAMETER
VC5510-200
UNIT
MIN MAX
SB1
SB2
SB3
SB4
SB5
SB6
SB9
SB10
SB11
SB12
SB13
SB14
SB15
SB16
td(CLKMEMH-CEL)
td(CLKMEMH-CEH)
td(CLKMEMH-BEV)
td(CLKMEMH-BEIV)
td(CLKMEMH-AV)
td(CLKMEMH-AIV)
td(CLKMEMH-ADSL)
td(CLKMEMH-ADSH)
td(CLKMEMH-OEL)
td(CLKMEMH-OEH)
td(CLKMEMH-DV)
td(CLKMEMH-DIV)
td(CLKMEMH-WEL)
td(CLKMEMH-WEH)
Delay time, CLKMEM high to CEx low
Delay time, CLKMEM high to CEx high
Delay time, CLKMEM high to BEx valid
Delay time, CLKMEM high to BEx invalid
Delay time, CLKMEM high to address valid
Delay time, CLKMEM high to address invalid
Delay time, CLKMEM high to SSADS low
Delay time, CLKMEM high to SSADS high
Delay time, CLKMEM high to SSOE low
Delay time, CLKMEM high to SSOE high
Delay time, CLKMEM high to data valid
Delay time, CLKMEM high to data invalid
Delay time, CLKMEM high to SSWE low
Delay time, CLKMEM high to SSWE high
3
6 ns
3
6 ns
3
6 ns
3
6 ns
3
6 ns
3
6 ns
3
6 ns
3
6 ns
3
6 ns
3
6 ns
3
6 ns
3
6 ns
3
6 ns
3
6 ns
August 2003 − Revised November 2003
SGUS045A
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